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| 5222-ds02-405-r 16215 alton parkway ? p.o. box 57013 ? irvine, ca 92619-7013 ? phone: 949-450-8700 ? fax: 949-450-8710 7/20/04 preliminary data sheet BCM5222 dual port 10/100base-tx ieee 8 02.3u fast ethernet transceiver figure 1: functional block diagram general description features the BCM5222 is a dual-port, low-power, 10/100base- tx transceiver targeting a number of applications requiring intelligent power management and robust network tolerance. the bcm5 222 operates using a 1.8v and 3.3v supply. the devices contain two full-duplex 10base-t/100base-tx fast ethernet transceivers, which perform all of the physical layer interface functions for 10base-t ethernet on cat 3, 4, and 5 unshielded twisted pair (utp) cable a nd 100base-tx fast ethernet on cat 5 utp cable. the BCM5222 is a highly integrated solution combining a digital adaptive equalizer, adc, phase lock loop, line driver, encoder, decoder and all the required support circuitry into a single mono lithic cmos chip. it complies fully with the ieee 802.3u specification, including the media independent interface (mii) and auto-negotiation subsections. the effective use of digital technology in the BCM5222 design results in robust performance over a broad range of operating scenarios. problems inherent to mixed- signal implementations, such as analog offset and on- chip noise, are eliminated by employing field proven digital adaptive equalization and digital clock recovery techniques. ? dual port 10/100base- tx ieee 802.3u fast ethernet transceiver ? power consumption: <180 mw/port ? unique energy detection circuit to enable intelligent power management ? hp auto-mdix ? cable length indication ? cable noise level indication ? cable length greater than 140 meters ? well under 10 ppm defect ratio quality ? industrial temperature range (-40 to 85c) ? mii/7-wire serial interface ? ieee 1149.1 (jtag) scan chain support ? mii management via serial port ? 100-pin pqfp and 100-pin fpbga packages applications ? ip phones ? backplane bus communication ? embedded telecom ? print servers mii mii equalizer auto-negotiation led clock bias registers mgmt control correction /link integrity generator generator wander baseline txd[1:2] txen[1:2] txer[1:2] txc[1:2] col[1:2] rxc[1:2] crs[1:2] rxdv[1:2] rxer[1:2] rxd[1:2] lnkled#[1:2] mdc mdio modes td [1:2] rd [1:2] xtalo recovery xmt dac adc spdled#[1:2] multimode digital adaptive 10base-t pcs 100base-tx pcs drivers clock xtali rdac actled#[1:2] detection crs/link 4 4 jtag test logic jtag 5 auto mdix fdxled#[1:2]
broadcom ? and the pulse logo are registered trademarks of broadcom corporation and/or its subsidiaries in the united states and certain other countries. all other trademarks mentioned are the property of their respective owners. this data sheet (including, without limit ation, the broadcom compon ent(s) identified herein) is not designed, intended, or certified for use in any military, nuclear, medical, mass transportation, aviation, navigations, pollution control, hazardous substances management, or other high risk application. broadcom provides this data sheet "as- is", without warranty of any kind. broadcom disclaims all warranties, expressed and implied, including, without li mitation, the implied warranti es of merchantabil ity, fitness for a particular purpose, and non-infringement. broadcom corporation p.o. box 57013 16215 alton parkway irvine, ca 92619-7013 ? 2003 by broadcom corporation all rights reserved printed in the u.s.a. r evision h istory revision date change description 5222-ds02-r 7/20/04 revised pin a ssignments, signal definitions, added new characterizations. 5222-ds01-r 10/12/01 updated clock information. 5222-ds00-r 3/1/01 initial release preliminary data sheet BCM5222 7/20/04 broadcom corporation document 5222-ds02-405-r page iii table of contents section 1: functional description ............... ................. .............. .............. .............. ............1 overview ............................................................................................................................... ........................ 1 encoder/decoder ............................................................................................................................... .......... 1 link monitor ............................................................................................................................... ................... 2 carrier sense ............................................................................................................................... ................. 2 collision detection ............................................................................................................................... ........ 2 auto-negotiation ............................................................................................................................... ........... 2 digital adaptive equalizer ........................................................................................................................... 3 adc ............................................................................................................................... ................................ 3 digital clock recovery/generator .............................................................................................................. 3 baseline wander correction ....................................................................................................................... 3 multimode transmit dac ............................................................................................................................ 3 stream cipher ............................................................................................................................... ................ 4 mii management ............................................................................................................................... ............ 4 section 2: hardware signal definitions ................ ................ ................. ................ ............6 section 3: pinout diagram ................ .............. .............. .............. .............. .............. .......... 10 section 4: operational description ................ .............. .............. .............. .............. .......... 12 reset ............................................................................................................................... ............................ 12 clock ............................................................................................................................... ............................ 12 isolate mode ............................................................................................................................... ................ 12 loopback mode ............................................................................................................................... ........... 12 full-duplex mode ............................................................................................................................... ........ 13 auto-mdix ............................................................................................................................... .................... 13 10base-t mode ............................................................................................................................... .......... 13 10base-t serial mode ............................................................................................................................... 14 special led modes ............................................................................................................................... ..... 14 force leds on .................................................................................................................. ................... 14 disable leds ................................................................................................................... ..................... 14 interrupt mode ............................................................................................................................... ............. 14 power saving modes ............................................................................................................................... .. 15 BCM5222 preliminary data sheet 7/20/04 broadcom corporation page iv document 5222-ds02-405-r section 5: register summary ................ ................ ................ ................. .............. ........... 16 media independent interface (mii) management interface: register programming ............................. 16 preamble (pre) ................................................................................................................. ................... 16 start of frame (st)............................................................................................................ .................... 16 operation code (op)............................................................................................................ ................. 16 phy address (phyad) ............................................................................................................ ............. 16 register address (regad)....................................................................................................... ............ 16 turnaround (ta) ................................................................................................................ .................... 17 data ........................................................................................................................... ............................17 idle........................................................................................................................... .............................. 17 mii control register ............................................................................................................................... ..... 17 reset .......................................................................................................................... ........................... 18 loopback ....................................................................................................................... ........................ 18 forced speed selection .............. ........................................................................................... ............... 18 auto-negotiation enable................................. ....................................................................... ................ 18 power down ..................................................................................................................... ..................... 19 isolate ........................................................................................................................ ............................ 19 restart auto-negotiation ......... .............................................................................................. ................ 19 duplex mode .................................................................................................................... ..................... 19 collision test ................................................................................................................. ........................ 19 reserved bits .................................................................................................................. ...................... 19 mii status register ............................................................................................................................... ...... 20 100base-t4 capability.. ................ ................ ................ ................ ................ ............. ........... ............... 20 100base-tx full-duplex capabilit y ................. ................ ................. ................ ................ ............ ....... 20 100base-tx half-duplex capability. ................ ................ ................. ................ ................ ............ ....... 20 10base-t full-duplex capability ................ ................ ................ ................ ................ ................ .......... 20 10base-t half-duplex capability .. ................ ................ ................ ................ ................. ............. ......... 21 reserved bits .................................................................................................................. ...................... 21 preamble suppression ...................................... ..................................................................... ............... 21 auto-negotiation comple te ...................................................................................................... ............. 21 remote fault ................................................................................................................... ...................... 21 auto-negotiation capability ..... ............................................................................................... ............... 21 link status.................................................................................................................... ......................... 21 jabber detect .................................................................................................................. ...................... 21 preliminary data sheet BCM5222 7/20/04 broadcom corporation document 5222-ds02-405-r page v extended capability ............................................................................................................ .................. 21 phy identifier registers ............................................................................................................................ 22 auto-negotiation advertisement register ............................................................................................... 22 next page ...................................................................................................................... ....................... 23 reserved bits.................................................................................................................. ...................... 23 remote fault ................................................................................................................... ..................... 23 reserved bits.................................................................................................................. ...................... 23 pause .......................................................................................................................... .......................... 23 advertisement bits ............................................................................................................. ................... 23 selector field ................................................................................................................. ....................... 23 auto-negotiation link partner (lp) ability register ............................................................................... 24 lp next page ................................................................................................................... ..................... 24 lp acknowledge ................................................................................................................. .................. 24 lp remote fault ................................................................................................................ ................... 24 reserved bits .................................................................................................................. .............. 24 lp advertise pause ............................................................................................................. .......... 24 lp advertise bits .............................................................................................................. ............. 25 lp selector field .............................................................................................................. ............. 25 auto-negotiation expansion register ...................................................................................................... 25 reserved bits.................................................................................................................. ...................... 25 parallel detection fault ......... .............................................................................................. .................. 25 link partner next page able.................................................................................................... ............. 25 next page able ................................................................................................................. .................... 26 page received.................................................................................................................. .................... 26 link partner auto-negotiation able............................................................................................. .......... 26 auto-negotiation next page register ...................................................................................................... 26 next page ...................................................................................................................... ....................... 26 message page ................................................................................................................... ................... 26 acknowledge 2.................................................................................................................. .................... 27 toggle ......................................................................................................................... .......................... 27 message code field ............................................................................................................. ................ 27 unformatted code field ..................................... .................................................................... ............... 27 auto-negotiation link partner (lp) next page transmit register ........................................................ 27 next page ...................................................................................................................... ....................... 27 message page ................................................................................................................... ................... 28 BCM5222 preliminary data sheet 7/20/04 broadcom corporation page vi document 5222-ds02-405-r acknowledge 2 .................................................................................................................. .................... 28 toggle......................................................................................................................... ........................... 28 message code field............................................................................................................. ................. 28 unformatted code field .................................... ..................................................................... ............... 28 100base-tx auxiliar y control register ................................................................................................... 28 transmit disable............................................................................................................... ..................... 29 bypass 4b5b encoder/decoder .................................................................................................... ........ 29 bypass scrambler/descrambler ................................................................................................... ......... 29 bypass nrzi encoder/decoder .................................................................................................... ........ 29 bypass receive symbol alignment................................................................................................ ....... 29 baseline wander correction disa ble............................................................................................. ........ 29 reserved bits .................................................................................................................. ...................... 29 100base-tx auxiliary status register .................................................................................................... 30 locked ......................................................................................................................... .......................... 30 current 100base-tx link status .. ................ ................ ................ ................ ................. .............. ........ 30 remote fault ................................................................................................................... ...................... 30 false carrier detected ................................... ...................................................................... ................. 30 bad esd detected ............................................................................................................... ................. 31 receive error detected .................................. ....................................................................... ................ 31 transmit error detected ........................................................................................................ ................ 31 lock error detected............................................................................................................ ................... 31 mlt3 code error detected ....................................................................................................... ............ 31 100base-tx receive error counter ......................................................................................................... 31 receive error counter [15:0]... ................................................................................................ .............. 31 100base-tx false carrier sense counter ............................................................................................... 32 false carrier sense counter [7:0].............................................................................................. ........... 32 auxiliary control/status register ............................................................................................................. 32 jabber disable................................................................................................................. ...................... 33 force link..................................................................................................................... ......................... 33 10m transmit power mode ........................................................................................................ ........... 33 hsq and lsq.................................................................................................................... .................... 33 edge rate...................................................................................................................... ........................ 33 auto-negotiation indication ..... ............................................................................................... ............... 33 force100/10 indication ......................................................................................................... ................. 33 speed indication............................................................................................................... ..................... 34 preliminary data sheet BCM5222 7/20/04 broadcom corporation document 5222-ds02-405-r page vii full-duplex indication ......................................................................................................... .................. 34 auxiliary status summary register ......................................................................................................... 34 interrupt register ............................................................................................................................... ........ 35 interrupt enable .......... ..................................................................................................... ..................... 35 fdx mask ....................................................................................................................... ...................... 35 spd mask ....................................................................................................................... ...................... 36 link mask ...................................................................................................................... ........................ 36 interrupt mask ................................................................................................................. ...................... 36 fdx change ..................................................................................................................... .................... 36 spd change ..................................................................................................................... .................... 36 link change .................................................................................................................... ...................... 36 interrupt status ............................................................................................................... ...................... 36 auxiliary mode 2 register ......................................................................................................................... 36 10bt dribble bit correct ....................................................................................................... ................ 37 jumbo packet enable ............................................................................................................ ............... 37 txc invert ..................................................................................................................... ........................ 37 block 10bt echo mode ........... ................................................................................................ ............. 37 qualified parallel detect mode ................................................................................................. ............ 37 10base-t auxiliary error and general status register ......................................................................... 38 mdix status .................................................................................................................... ...................... 38 mdix manual swap ............................................................................................................... ............... 38 hp auto-mdix disable ........................................................................................................... .............. 38 manchester code error.. ........................................................................................................ ............... 39 end of frame error ............................................................................................................. .................. 39 auto-negotiation indication ...... .............................................................................................. ............... 39 force 100/10 indication ........................................................................................................ ................ 39 speed indication ............................................................................................................... .................... 39 full-duplex indication ......................................................................................................... .................. 39 auxiliary mode register ............................................................................................................................ 40 link led disable ............................................................................................................... ................... 40 block txen mode................................................................................................................ ................. 40 auxiliary multiple phy register ................................................................................................................ 40 hcd bits ....................................................................................................................... ........................ 41 restart auto-negotiation.......... ............................................................................................. ................ 41 auto-negotiation comple te ...................................................................................................... ............. 41 BCM5222 preliminary data sheet 7/20/04 broadcom corporation page viii document 5222-ds02-405-r acknowledge complete........................................................................................................... .............. 41 acknowledge detected........................................................................................................... ............... 41 ability detect................................................................................................................. ......................... 42 super isolate .................................................................................................................. ....................... 42 10base-t serial mode ............... ................ ................ ................ ................ ................ ............ .............. 42 broadcom test register ............................................................................................................................ 42 shadow register enable ......................................................................................................... .............. 42 auxiliary mode 4 register (shadow register) ......................................................................................... 43 force led [1:0] ................................................................................................................ ..................... 43 enable clock during low power .......................... ........................................................................ .........43 force iddq mode ................................................................................................................ ................. 43 auxiliary status 2 register (shadow register) ........................................................................................ 44 mlt3 detected .................................................................................................................. .................... 44 cable length 100x [2:0]................................. ....................................................................... ................ 44 adc peak amplitude [5:0]................................. ...................................................................... .............. 44 auxiliary status 3 register (shadow register) ........................................................................................ 45 noise [7:0] .................................................................................................................... ......................... 45 fifo consumption [3:0] ......................................................................................................... ............... 45 auxiliary mode 3 register (shadow register) ......................................................................................... 45 fifo size select [3:0] ......................................................................................................... .................. 45 auxiliary status 4 register (shadow register) ........................................................................................ 46 packet length counter [15:0]................................................................................................... ............. 46 section 6: timing a nd ac characteristics ................. .............. .............. .............. ........... 47 section 7: electri cal characteristics ................ ................. ................ ................. ............. 58 section 8: appl ication example ................. ................. .............. .............. .............. ........... 60 section 9: mechanical information ................. .............. .............. .............. .............. ......... 61 section 10: ordering information ................. .............. .............. .............. .............. ........... 63 preliminary data sheet BCM5222 7/20/04 broadcom corporation document 5222-ds02-405-r page ix l ist of f igures figure 1: functional block dia gram ............................................................................................. ........................i figure 2: BCM5222kqm pinout diagram .............. .............................................................................. ............ 10 figure 3: BCM5222kpf pinout dia gram............................................................................................ .............. 11 figure 4: clock and reset timing ............................................................................................... ..................... 47 figure 5: mii transmit start of packet timing (1 00base-tx) ................ ................ ............. ............ ............ .... 48 figure 6: mii transmit end of packet timing (100 base-tx) ............. ................ ................. ............ ............. ... 49 figure 7: mii receive start of pa cket timing (100base-tx ) ................. ................ ............. ............ ............ .... 50 figure 8: mii receive en d of packet timing (100base- tx................ ................ ................. ............ ............ .... 51 figure 9: mii receive packet prem ature end (100base-tx) ... ................ ................ ............. ............. ........... .51 figure 10: mii link failure or stre am cipher error during receive packet. .................................................... 52 figure 11: mii false carrier sens e timing (100base-tx).... ................. ................ ............. ............ ........... ..... 52 figure 12: mii 10base-t transmit st art of packet timing . ................ ................ ............. ............. ............. ...... 53 figure 13: 10base-t serial transmit timing ........ ............................................................................. ............. 55 figure 14: 10base-t serial receive timing ...................................................................................... ............. 56 figure 15: management interface timing......................................................................................... ................ 57 figure 16: management interf ace timing (with preamble suppression on).................................................... 57 figure 17: BCM5222 1.8v and 3.3v power connections in 100 mqfp pack age ........................................... 60 figure 18: 100-pin mqfp package................................................................................................ .................. 61 figure 19: 100-pin fbga package ..................... ........................................................................... .................. 62 BCM5222 preliminary data sheet 7/20/04 broadcom corporation page x document 5222-ds02-405-r l ist of t ables table 1: 4b5b encoding ......................................................................................................... ............................ 4 table 2: receive error encoding ..................... ........................................................................... ........................ 5 table 3: pin descriptions ................................. ..................................................................... .............................. 6 table 4: 10base-t serial mode (7-wire) signals .. ............................................................................... ........... 14 table 5: low power modes ....................................................................................................... ....................... 15 table 6: mii management frame format ........................................................................................... .............. 16 table 7: mii control register (address 00000b, 0d , 00h) ........................................................................ ........ 17 table 8: mii status register (address 00001b, 01d, 01h) ........................................................................ ....... 20 table 9: phy indentifier registers (a ddresses 00010 and 000 11b, 02 and 03b, 02 and 03h) ........................ 22 table 10: auto-negotiation advertisem ent register (address 04d, 04h) ......................................................... 22 table 11: auto-negotiation link part ner ability register (address 05d, 05h) .................................................. 24 table 12: auto-negotiation expansio n register (address 00110b, 6d, 06h) ................................................... 25 table 13: next page transmit register (address 07 d, 07h) ....................................................................... ..... 26 table 14: next page transmit register (address 08 d, 08h) ....................................................................... ..... 27 table 15: 100base-tx auxiliary control register (addre ss 16d, 10h)......... ................ ............. ............ .......... 2 8 table 16: 100base-x auxiliary status register (addre ss 17d, 11h) ........ ................ ............. ............. ............. 30 table 17: 100base-tx receive error counter (address 18d, 12h) ............. ................ ............. ............ .......... 31 table 18: 100base-tx false carrier sense counter (address 19d, 13h) ... ................ ............. ............ .......... 32 table 19: auxiliary control/status register (address 11000b, 24d, 18h)......................................................... 32 table 20: auxiliary status summary register (address 11001b, 25d, 19h) ..................................................... 34 table 21: interrupt register (address 26d, 1ah) . ............................................................................... ..............35 table 22: auxiliary mode 2 regist er (address 27d, 1bh) ......................................................................... ........ 36 table 23: 10base-t auxiliary error & ge neral status register (address 28d, 1ch)....... ............. ............. ...... 38 table 24: auxiliary mode register (address 11101b, 29d, 1dh) ................................................................... ... 40 table 25: auxiliary multiple phy register (address 30 d, 1eh) ................................................................... ..... 40 table 26: broadcom test (address 31d, 1fh) ..................................................................................... ............. 42 table 27: auxiliary mode 4 register (shadow register 26d, 1ah) ................................................................. .. 43 table 28: auxiliary status 2 register (shadow regist er 27d, 1bh)............................................................... ... 44 table 29: cable length......................................................................................................... ............................ 44 table 30: auxiliary status 3 register (shadow regist er 28d, 1ch)............................................................... ... 45 table 31: auxiliary mode 3 register (shadow register 29d, 1dh)................................................................. .. 45 table 32: current receive fifo size ............................................................................................ ................... 45 preliminary data sheet BCM5222 7/20/04 broadcom corporation document 5222-ds02-405-r page xi table 33: auxiliary status 4 register (shadow regist er 30d, 1eh) ............................................................... .. 46 table 34: clock timing......................................................................................................... ............................ 47 table 35: reset timing ......................................................................................................... ........................... 47 table 36: mii 100base-tx transmit timing ................ ................ ................ ............. ............. ............. ............ 48 table 37: mii 100base-tx receive ti ming .......... ................ ................. ................ ................ ............. ............ 49 table 38: mii 10base-t tran smit timing........ ................ ................ ............. ............. ............. .......... ............... 53 table 39: mii 10base-t receive timi ng............... ................ ................. ................ ................ .......... ............... 54 table 40: mii 10base-t collision ti ming ........... ................ ................ ................ ................. ............ ................ 54 table 41: 10base_t serial transmit timing................ ................ ................ ............. ............. ............ ............. 54 table 42: 10base_t serial receive timing............. ................. ................ ................ ............. ............ ............. 55 table 43: loopback timing ...................................................................................................... ........................ 56 table 44: auto-negotiation timing .............................................................................................. ..................... 56 table 45: led timing........................................................................................................... ............................ 56 table 46: management data interface timing ....... .............................................................................. ............ 57 table 47: absolute maximum ratings.................... ......................................................................... ................. 58 table 48: recommended operating cond itions for BCM5222 ........................................................................ 5 8 table 49: package thermal characteristics (BCM5222 kqm) ......................................................................... 58 table 50: package thermal characteristics (BCM5222 kpf) ......................................................................... .58 table 51: electrical characteristics ........................................................................................... ....................... 59 BCM5222 preliminary data sheet 7/20/04 broadcom corporation page xii document 5222-ds02-405-r preliminary data sheet BCM5222 7/20/04 broadcom corporation document 5222-ds02-405-r functional description page 1 section 1: functional description o verview the BCM5222 is a dual-port, single-chip fast ethernet transcei ver. it performs all of the ph ysical layer interface functions for 100base-tx full-or ha lf-duplex ethernet on cat 5 t wisted pair cable and 10 base-t full-or half-dupl ex ethernet on cat 3, 4, or 5 cable. the chip performs 4b5b, mlt3, nrzi, and manchester encoding and decoding, clock and data recovery, stream cipher scrambling/descrambling, digital adaptive equalization, line tr ansmission, carrier sense and link integrity monitor, auto- negotiation and media independent interface (mii) management f unctions. each of the two phys in the BCM5222 can be connected to a mac switch controller th rough the mii on one side, and can connect directly to the network media on the other side (through isolation transformers for unshielded twisted pair (utp)). the BCM5222 is fully compliant with the ieee 802.3 and 802.3u standards. e ncoder /d ecoder in 100base-tx mode, the BCM5222 transmit s and receives a continuous data stream on twisted-pair cable. when the mii transmit enable is asserted, nibble-wid e (4-bit) data from the transmit data pins is encoded into 5-bit code groups and inserted into the transmit data stream. the 4b5b encoding is shown in table 1 on page 4 . the transmit packet is encapsulated by replacing the first 2 nibbles of preamble wi th a start of stream delimiter (j/k codes) and appending an end of stream delimiter (t/r codes) to the end of the packet. wh en the mii transmit error input is asserted during a packet, the transmit error code group (h) is sent in place of the corre sponding data code group. the transmitter repeatedly sends the idle code group between packets. in 100base-tx mode, the encoded data str eam is scrambled by a stream cipher block and then serialized and encoded into mlt3 signal levels. a multi-mode transmit dac is us ed to drive the mlt3 data onto the twisted pair cable. following baselin e wander correctio n, adaptive equalization, an d clock recovery in 100base- tx mode, the receive data stream is converted fr om mlt3 to serial nrz data. the nrz data is descrambled by the stream cipher block and then deserialized and aligned into 5-bit code groups. the 5-bit code groups are decoded into 4-bit data nibbles, as shown in table 1 . the start of stream de limiter is replaced with preamble nibbles and the end of stream del imiter and idle codes are replaced with al l zeros. the decoded data is driven onto the mii receive data pins. when an invalid code group is det ected in the data stream, the BCM5222 asserts the mii rxer signal. the chip also asserts rxer for several other error co nditions that improperly terminate the data stream. while rxer is asserted, the receive data pins are driv en with a 4-bit code indicating the type of error detected. the error codes are list ed in table 2 on page 5 . in 10base-t mode, manchester en coding and decodi ng is performed on the data str eam. the multimode transmit dac performs pre-equalization for 100 meters of cat 3 cable. BCM5222 preliminary data sheet 7/20/04 broadcom corporation page 2 link monitor document 5222-ds02-405-r l ink m onitor in 100base-tx mode, receive signal energy is detected by moni toring the receive pair for transitions in the signal level. signal levels are qualified using squelch detect circuits. when no signal or certain invalid signals are detected on the receiv e pair, the link monitor enters and remains in the link fail state, where only idle codes are transmitted. when a valid signal is detected on the receive pair for a minimu m period of time, the link monitor enters the link pass state and the transmit and receive functions are enabled. in 10base-t mode, a link-puls e detection circuit cons tantly monitors the rd pins for the presence of valid link pulses. c arrier s ense in 100base-tx mode, carrier sense is asserted asynchronously on the crs pin as soon as activi ty is detected in the receive data stream. rxdv is asserted as soon as a valid start-of-str eam delimiter (ssd) is detected. carrier sense and rxdv are deasserted synchronously upon detection of a valid end of stream delimiter or tw o consecutive idle code groups in the receive data stream. if carrier sense is asserted and a valid ssd is not detected immediately, th en rxer is asserted in place of rxdv. a value of 1110 is driven on the receiv e data pins to indicate false carrier sense. in 10base-t mode, carrier sense is asserted asynchronously on the crs pin when valid preamble activity is detected on the rd input pins. in half-duplex dte mode, the BCM5222 asserts carrier sense while transmit enable is asserted and the link monitor is in the pass state. in full-duplex mode, crs is only asserted for receive activity. c ollision d etection in half-duplex mode, collision detect is asserted on the col pin whenever carrier sense is asserted and transmission is in progress. a uto -n egotiation the BCM5222 contains the ability to negotia te its mode of operation over the t wisted pair link using the auto-negotiation mechanism defined in the ieee 802.3u specif ication. auto-negotiation can be enabled or disabled by hardware or software control. when the auto- negotiation function is enabled, the BCM5222 autom atically chooses its mode of operation by advertising its abilities and comparing them with those re ceived from its link partner. the BCM5222 has next page capabilities. the next page and auto-negotiation must be enable d. once auto-negotiation begins the pages are to be sent by writing to register 7 for each page. the BCM5222 can be configured to advertise 100base-tx fu ll-duplex and/or half-duple x and 10base-t fu ll-and/or half- duplex. the transceiver negotiates with its link partner and choo ses the highest level of operation available for its own link. preliminary data sheet BCM5222 7/20/04 broadcom corporation document 5222-ds02-405-r digital adaptive equalizer page 3 d igital a daptive e qualizer the digital adaptive equalizer removes intersymbol interferenc e (isi) created by the trans mission channel media. the equalizer accepts sampled unequalized data from the adc on each channel and produces equalized data. the BCM5222 achieves an optimum signal-to-noise ratio by using a co mbination of feed forward equalization and decision feedback equalization. this powerful technique achieves a 100base- tx ber of less than 1 x 10 -12 for transmission up to 100 meters on cat 5 twisted pair cable, even in harsh noise environmen ts. the digital adaptive equalizers in the BCM5222 achieve performance close to theoretical limits. the all-digital nature of the design makes the performance very tolerant to on-chip noise. the filter coefficients are self-adapting to any qualit y of cable or cable length. d ue to transmit pre-equalization in 10base-t mode, the ada ptive equalizer is bypassed in these two modes of operation. adc the receive channel has a 6-bit, 125-mhz analog-to-digital co nverter (adc). the adc samples the incoming data on the receive channel and produces a 6-bit output . the adc output is fed to the digital adaptive equalizer. advanced analog circuit techniques achieve low-offset, high-po wer-supply noise rejection, fast-set tling time, and low-bit error rate. d igital c lock r ecovery /g enerator the all-digital clock recovery a nd generator block create s all internal transmit and receive clocks. the transmit clock is lock ed to the 25-mhz clock input, while the receive clock is locked to the incoming data stream. clo ck recovery circuits optimized to mlt3 and manchester encoding schemes are included for us e with the different operating modes. the input data stream is sampled by the recovered clock, and fed sy nchronously to the digital adaptive equalizer. b aseline w ander c orrection a 100base-tx data stream is not always dc balanced. because the receive signal must pass through a transformer, the dc offset of the differential receive inpu t can wander. this effect, known as baseline wander, can greatly reduce the noise immunity of the receiver. the BCM5222 automatically compensate s for baseline wander by removing the dc offset from the input signal, and thereby significantly reduces the chance of a receive symbol error. the baseline wander correction circuit is not required, and therefore is bypassed, in 10base-t operating mode. m ultimode t ransmit dac the multimode transmit digital-to-analog converter (d ac) transmits mlt3-coded sym bols in 100base-tx mode and manchester-coded symbols in 10base-t mode. it allows progr ammable edge-rate control in tx mode, which decreases unwanted high frequency signal components, thereby reduc ing emi. high-frequency pre-emphasis is performed in 10base-t mode. the transmit dac utilizes a current drive output, which is we ll balanced, and pro duces very low noise transmit signals. BCM5222 preliminary data sheet 7/20/04 broadcom corporation page 4 stream cipher document 5222-ds02-405-r s tream c ipher in 100base-tx mode, the transmit data st ream is scrambled to reduce radiated emissions on the twisted-pair cable. the data is scrambled by exclusive oring the nrz signal with the output of an 11-bit-wide linear feedback shift register (lfsr), which produces a 2047-bit non-repeating sequence. the scrambler reduces peak em issions by randomly spreading the signal energy over the transmit frequency rang e and eliminating peaks at certain frequencies. the receiver descrambles the incoming data stream by exclusive oring it with the same sequence generated at the transmitter. the descrambler detects the state of the transmit lfsr by looking fo r a sequence representing consecutive idle codes. the descrambler locks to the scrambl er state after detecting a sufficient nu mber of consecutive idle code-groups. the receiver does not attempt to decode the data stream unl ess the descrambler is locked. when locked, the descrambler continuously monitors the data stream to make sure that it has not lost synchronization. the receive data stream is expected to contain inter-packet idle periods. if the descram bler does not detect enough idle codes within 724 s, it becomes unlocked, and the receive decoder is disabled. the descrambler is alwa ys forced into the unlocked state when a link failure condition is detected. stream cipher scrambling/descrambl ing is not used in 10base-t mode. mii m anagement the BCM5222 contains two complete sets of mii management registers accessible by using the management clock line (mdc) and the bidirectional serial data line (mdio). each phy has one associated mii regi ster which is accessed by commands containing the corresponding phy address. by conf iguring the five external phy address input pins, the phy address of phy 1 is set. phy 2 address will be one bit higher than that of phy 1. every time an mii read or write operation is executed, th e BCM5222 compares the operation's phy address with its own phy address definition. the operation is executed only when the addresses match. for further details, see section 5: ?register summary? on page 16 . table 1: 4b5b encoding name 4b code 5b code meaning 0 0000 11110 data 0 1 0001 01001 data 1 2 0010 10100 data 2 3 0011 10101 data 3 4 0100 01010 data 4 5 0101 01011 data 5 6 0110 01110 data 6 7 0111 01111 data 7 8 1000 10010 data 8 9 1001 10011 data 9 a 1010 10110 data a b 1011 10111 data b preliminary data sheet BCM5222 7/20/04 broadcom corporation document 5222-ds02-405-r mii management page 5 c 1100 11010 data c d 1101 11011 data d e 1110 11100 data e f 1111 11101 data f i 0000* 11111 idle j 0101* 11000 start-of-stream delimiter, part 1 k 0101* 10001 start-of-stream delimiter, part 2 t 0000* 01101 end-of-stream delimiter, part 1 r 0000* 00111 end-of-stream delimiter, part 2 h 1000 00100 transmit error (used to force signalling errors) v 0111 00000 invalid code v 0111 00001 invalid code v 0111 00010 invalid code v 0111 00011 invalid code v 0111 00101 invalid code v 0111 00110 invalid code v 0111 01000 invalid code v 0111 011000 invalid code v 0111 10000 invalid code v 0111 11001 invalid code * treated as invalid code (mapped to 0111) when received in data field. table 2: receive error encoding error type rxd[3:0] stream cipher error?descrambler lost lock 0010 link failure 0011 premature end of stream 0110 invalid code 0111 transmit error 1000 false carrier sense 1110 table 1: 4b5b encoding (cont.) name 4b code 5b code meaning BCM5222 preliminary data sheet 7/20/04 broadcom corporation page 6 hardware signal definitions document 5222-ds02-405-r section 2: hardware signal definitions table 3 provides the pin descriptions for the BCM5222 bga and mqfp packages. table 3: pin descriptions bga mqfp pin label type description media connections k5, k6 k4, k7 38, 44 37, 45 rd+{2}, rd+{1} rd ? {2}, rd-{1} i/o receive pair . differential data from the media is received on the rd signal pair. this pair will function as tx in the mdix configuration. k2, k9 k3, k8 35, 47 36, 46 td+{2}, td+{1} td ? {2}, td-{1} i/o transmit pair. differential data is tran smitted to the media on the td signal pair. this pair will function as rx in the mdix configuration. clock h3, h4 33 32 xtali xtalo i/o crystal input, output. a continuous 25 mhz reference clock must be supplied to the BCM5222 by connecting a 25 mhz crystal between these two pins or by driving xtali with an external 25 mhz clock. when using a crystal, connect a loading capacitor from each pin to ground. when using an oscillator, leave xtalo unconnected. mii interface a2, c7 97, 84 txc{2}, txc{1} o 3s transmit clock. 25-mhz output in 100base-tx mode and 2.5 mhz in 10base-t mii mode . 10-mhz output in 10base- t serial mode. this clock is a continuously driven output, generated from the xtali input. d5, a8 a3, b7 d6, a7 a4, c6 96, 85 95, 86 94, 87 93, 88 txd3{2}, txd3{1} txd2{2}, txd2{1} txd1{2}, txd1{1} txd0{2}, txd0{1} i pd mii transmit data input. nibble-wide transmit data stream is input on these pins synchronous with txc. txd3 is the most significant bit. only txd0 is used in 10base-t serial mode. c5, a9 98, 83 txen {2}, txen{1} i pd mii transmit enable. active high. indicates that the data nibble on txd[3:0] is valid. g8, e10 62, 65 tdi/txer{2}, tms/ txer{1} i pd mii transmit error. an active high input is asserted when a transmit error condition is requested by the mac. c2, d9 8, 73 rxc{2}, rxc{1} o 3s mii receive clock. 25-mhz output in 100base-tx mii mode and 2.5-mhz output in 10base-t mii mode. 10-mhz output in 10base-t serial mode. this clock is recovered from the incoming data on the cable inputs. rxc is a continuously running output clock resynchronized at the start of each incoming packet. this synchroni zation may result in an elongated period during one cycle while rxdv is low. a1, d7 b2, a10 c3, c9 b1, d8 2, 79 3, 78 4, 77 5, 76 rxd3{2}, rxd3{1} rxd2{2}, rxd2{1} rxd1{2}, rxd1{1} rxd0{2}, rxd0{1} o 3s mii receive data outputs. nibble-wide receive data stream is driven out on these pins synchronous with rxc. rxd3 is the most significant bit. on ly rxd0 is used in 10base-t serial mode. d4, b10 6, 75 rxdv{2}, rxdv{1} o 3s mii receive data valid. active high. indicates that a receive frame is in progress, and that the data stream present on the rxd output pins is valid. [msb:lsb]; overline = active-low signal, i = input, o = output, i/o = bidirectional, i pu = input w/ internal pull-up, o od = open-drain output, o 3s = three-state output, b = bias, pwr = power supply, gnd = ground preliminary data sheet BCM5222 7/20/04 broadcom corporation document 5222-ds02-405-r hardware signal definitions page 7 c1, e6 7, 74 rxer{2}, rxer{1} o 3s mii receive error detected. active high. indicates that an error is occurring during a receive frame. e5, c10 9, 72 crs{2}, crs{1} o 3s mii carrier sense. active high. indicates traffic on link. in 100base-tx mode, crs is asserted when a non-idle condition is detected in t he receive data stream and deasserted when idle or a valid end of stream delimiter is detected. in 10base-t mode, cr s is asserted when a valid preamble is detected and dea sserted when end-of-file or an idle condition is detected. crs is also asserted during transmission of packets except in full-duplex modes. crs is an asynchronous output signal. d3, e7 10, 71 col{2}, col{1} o 3s collision detect. in half-duplex modes, active high output indicates that a collision has occurred. in full-duplex mode, col remains low. col is an asynchronous output signal. a5 91 mdio i/o pu management data i/o. this serial input/output bit is used to read from and write to the mii registers of each of the phys. the data value on the mdio pin is valid and latched on the rising edge of mdc. b5 92 mdc i pd management data clock. the mdc clock input must be provided to allow mii management functions. clock frequencies up to 25 mhz are supported. mode d10 68 reset i pu reset. active low. resets the BCM5222. also used to enable power off and low power modes. e1, e4 13, 14 phyad0, phyad1, i pu phy address selects phyad[1:0]. these inputs set the two least significant bits of the mii management phy address for phy 1. phy 2 address will be one greater than the phy 1 address.these pins are sampled only during power-on reset. e3, e2, f1 15, 16, 17 phyad2, phyad3, phyad4 i pd phy address selects phyad[4:2]. these inputs set the three most significant bits of the mii management phy address for phy 1. phy 2 address will be one greater than the phy 1 address.these pins are sampled only during power-on reset. h8 f9 51, 64 pause{2}, tdo/pause{1} o pd pause. status of the li nk partner?s pause bit, bit 10d of mii link partner ability register 05d. f6 63 tck/fdx i pu full-duplex mode. when auto-negotiation is disabled, the fdx pin is logically ored with re gister 00, bit 8 to select full- duplex (1) or half-duplex (0) operation. (this pin becomes tck if trst pin is high.) when auto- negotiation is enabled, this pin is ignored. h2 27 low_pwr i pd low power mode enable. active high input places the BCM5222 into low power operation with the chip deactivated except for the crystal oscillator if bit 2 of shadow register 1ah is set to the non-default value of 1. when asserted with reset pulled low, the entire chip is deactivated (power off mode). table 3: pin descriptions (cont.) bga mqfp pin label type description [msb:lsb]; overline = active-low signal, i = input, o = output, i/o = bidirectional, i pu = input w/ internal pull-up, o od = open-drain output, o 3s = three-state output, b = bias, pwr = power supply, gnd = ground BCM5222 preliminary data sheet 7/20/04 broadcom corporation page 8 hardware signal definitions document 5222-ds02-405-r j1 25 f100 i pu force 100base-tx control. when f100 is high and anen is low, the transceiver is fo rced to 100base -tx operation. when f100 is low and anen is low, the transceiver is forced to 10base-t operation. when an en is high, f100 has no effect on operation. g2 24 anen i pu auto-negotiation enable. anen is active high. when pulled high, auto-negotiation begins immediately after reset. when low, auto-negotiation is disabled by default. f7 67 testen i pd test mode enable. active high. can float or be grounded for normal operation. j7, h9 53, 54 adv_pause{2}, adv_pause{1} i pu adv_pause. active low. during power-on reset, this pin is sampled and causes the default value of mii auto-negotiation advertisement register, 4, bit 10d to be set accordingly. j10 52 mdix_dis i pd hp auto-mdix disable. active high. during power-on reset if this pin is high the BCM5222 disables mdi cable cross-over detection on both ports. a6 89 intr o 3s interrupt. when the interrupt mode is enabled, pin becomes intr . this pin is shared by both phy 1 and phy 2. k10 50 dlltest i pu dll test. this pin must be left unconnected during normal operation. bias g4 29 rdac b dac bias resistor. adjusts the current le vel of the transmit dac. a resistor of 1.31 k ? 1% must be connected between the rdac pin and gnd. leds f5, g9 18, 60 lnkled {2}, lnkled {1} o 3s link integrity led. the link integrity led indicates the link status of the phy. lnkled is driven low when the link to the phy is good. f2, g7 20, 58 spdled {2}, spdled {1} o 3s 100base-tx led. the 100 base-tx led is driven low when operating in 100base-tx modes and high when operating in 10base-t modes. f3, g6 21, 57 fdxled {2}, fdxled {1} o 3s full-duplex led. driven low when the link is full-duplex and driven high in half-duplex. f4, g10 19, 59 actled {2}, actled {1} o 3s activity led. active low output. the receive activity led is driven low for approximately 80 ms each time there is receive or transmit activity, while in the link pass state. jtag f8 66 trst i pd test reset. must be set low for normal operation, holding the jtag circuitry in reset. transition from low to high initializes the jtag tap controller to the test-logic-reset state. hold high during jtag. f6 63 tck/fdx i pu test clock. this pin becomes tck if trst pin is high. clock input used to synchronize jtag tap control and data transfers. g8 62 tdi/txer{2} i pd test data input. this pin becomes tdi if trst is high. data or instruction input for jtag te st logic. sampled on the rising edge of tck. table 3: pin descriptions (cont.) bga mqfp pin label type description [msb:lsb]; overline = active-low signal, i = input, o = output, i/o = bidirectional, i pu = input w/ internal pull-up, o od = open-drain output, o 3s = three-state output, b = bias, pwr = power supply, gnd = ground preliminary data sheet BCM5222 7/20/04 broadcom corporation document 5222-ds02-405-r hardware signal definitions page 9 e10 65 tms/txer{1} i pd test mode select. this pin becomes tms if trst is high. single control input to the jtag tap controller is used to traverse the test-logic state machine. sampled on the rising edge of tck. f9 64 tdo/pause{1} o 3s test data output. this pin becomes tdo if trst is high. serial data output from the jtag tap controller. updated on the falling edge of tck. power b8, c4 99, 82 dvdd pwr digital vdd (1.8v). connect these pins to decoupling capacitors as shown in figure 17 on page 60. j5 41 avdd pwr analog vdd (1.8v). connect this pin to decoupling capacitors as shown in figure 17 on page 60. b3, c8, d1, e8, g1, h10 1, 11, 22, 56, 70, 80 ovdd pwr 3.3v digital periphery (output buffer) vdd supply. b6, b4, b9 100, 90, 81 dgnd gnd digital ground. g5, j6, h5, h6 39, 40, 42, 43 agnd gnd analog ground. j2 28 biasvdd pwr bias vdd (3.3v). connect this pin to decoupling capacitors as shown in figure 17 on page 60. j3 30 biasgnd gnd bias ground. connect this pin to agnd. h7, h1, d2, e9 12, 23, 55, 69 ognd gnd output buffer ground. digital periphery (output buffer) ground. j4 34 pllagnd gnd pll analog ground. phase locked loop ground. k1 31 pllavdd pwr pll analog vdd (1.8v). 1.8v, phase locked loop vdd core. connect this pin to decoupling capacitors as shown in figure 17 on page 60 . no connects j8, j9 g3, f10 26, 48, 49, 61 nc nc no connection. leave these pins floating. table 3: pin descriptions (cont.) bga mqfp pin label type description [msb:lsb]; overline = active-low signal, i = input, o = output, i/o = bidirectional, i pu = input w/ internal pull-up, o od = open-drain output, o 3s = three-state output, b = bias, pwr = power supply, gnd = ground BCM5222 preliminary data sheet 7/20/04 broadcom corporation page 10 pinout diagram document 5222-ds02-405-r section 3: pinout diagram figure 2 provides the pinout diagram for the BCM5222kqm package, and figure3onpage11 provides the pinout diagram for the BCM5222kpf package. figure 2: BCM5222kqm pinout diagram txd1{2} txd0{2} txd2{1} txd1{1} txd2{2} txd3{2} txen{2} txc{2} intr# txd0{1} dgnd dvdd mdc mdio nc ovdd crs{2} pause{2} rxd3{2} rxd2{2} rxd1{2} rxd0{2} rxer{2} rxc{2} biasvdd low_pwr anen f100 ognd BCM5222 2 1 4 3 6 5 8 7 10 9 12 11 14 13 16 15 98 100 96 97 94 95 92 93 90 91 99 89 87 88 85 86 (100 pins pqfp) rxdv{2} ovdd rxer{1} rxc{1} ognd rxd3{1} rxd2{1} rxd1{1} col{1} rxdv{1} rxd0{1} tck/fdx nc tdi/txer{2} crs{1} reset# 78 79 80 77 70 62 76 64 74 75 63 69 72 71 61 73 pllavdd pllagnd dlltest td+{2} agnd nc rd-{2} rd +{2} td-{2} agnd avdd xtalo agnd agnd nc td+{1) 32 31 34 33 36 35 38 37 40 39 42 41 44 43 46 45 biasgnd rdac 18 17 20 19 td -{1} rd -{1} rd+{1} xtali 48 47 50 49 tdo/pause{1} testen tms/txer{1} trst# 66 68 67 65 dvdd txen{1} txd3{1} txc{1} 83 84 81 82 dgnd col{2} ovdd ovdd dgnd 22 21 24 23 26 25 28 27 30 29 58 59 60 57 56 54 55 52 51 53 lnkled#{2} spdled#{2} fdxled#{2} actled#{2} lnkled#{1} spdled#{1} fdxled#{1} actled#{1} ognd ovdd adv_pause{1} adv_pause{2} ovdd ognd phyad0 phyad1 phyad2 phyad3 phyad4 mdix_dis preliminary data sheet BCM5222 7/20/04 broadcom corporation document 5222-ds02-405-r pinout diagram page 11 figure 3: BCM5222kpf pinout diagram rxd3{2} txc{2} txd2{2} txd0{2} mdio intr txd1{1} txd3{1} txen{1} rxd0{2} rxd2{ 2} ov dd dgnd mdc dgnd txd2{1} dv dd dgnd rxer{2} rxc{2} rxd1{2} dvdd txen{2} txd0{1} txc{1} ovdd rxd1{1} ovdd ognd col{2} rxdv{2} txd3{2} txd1{2} rxd3{1} rxd0{1} rxc{1} phy a d0 phy a d3 phy a d2 phy a d1 crs{2} rxer{1} col{ 1} ov dd ognd phy a d4 spdled{2} fdxled{2} actled{2} lnkled{2} tck fdx testen trst tdo pause{1} ov dd a nen nc rda c a gnd fdxled{1} spdled{1} tdi txer{2} lnkled{1} ognd low_pwr xtali xtalo agnd agnd ognd pause{2} adv_ pause{1} f100 biasvdd biasgnd pllagnd avdd agnd adv_ pause{2} nc nc pllavdd td+{2} td-{2} rd-{2} rd+{2} rd+{1} rd-{1} td-{1} td+{1} a b c d e f g h j k 2 1 3456789 a b c d e f g h j k 2 1 3456789 10 10 tms txer{1} rxd2{ 1} rxdv {1} crs{ 1} reset mdix_dis ov dd actled{1} nc dlltest BCM5222 preliminary data sheet 7/20/04 broadcom corporation page 12 operational description document 5222-ds02-405-r section 4: operational description r eset there are two ways to reset the BCM5222. a hardware reset pin is provided that resets all internal nodes in the chip to a known state. the reset pulse must be asserted for at least 400 ns. hardware reset should always be applied to the BCM5222 after power-up. the BCM5222 also has a software reset capability. to perform soft ware reset, a 1 must be written to bit 15 of the mii control register. this bit is self-clearing, meanin g that a second write operat ion is not necessary to end the reset. there is no effec t if a 0 is written to the mii control register reset bit . c lock the BCM5222 requires a 25 mhz clock reference which can be driven by attaching a 25 -mhz crystal between the xtali and xtalo pins or by connecting an external oscillator to pin xtali. connect 22 pf capacitors from each pin to ground when using a crystal. when using an oscillator, leave xtalo unconn ected. the reference clock requ ires accuracy of at least 50 ppm. i solate m ode when the BCM5222 is put into isolate mode, all mii inputs (txd[3:0], txen, and txer) are ignored, and all mii outputs (txc, col, crs, rxc, rxdv, rxer, a nd rxd[3:0]) are set to high impedance. only the mii management pins (mdc, mdio) operate normally. upon resetting the chip , the isolate mode is off. writing a 1 to bit 10 of the mii control register put s the transceiver into isolate mode. writing a 0 to the same bit removes it from isolate mode. l oopback m ode loopback mode allows in-circuit testing of the BCM5222 chip. all packets sent in through the txd pins are looped-back internally to the rxd pins, and are not sent out to the cable. the loopba ck mode is enabled by writing a 1 to bit 14 of the mii control register. to resume no rmal operation, bit 14 of the mii control register must be 0. incoming packets on the cable are ignored in loopback mode. be cause of this, the col pin is normally not activated during loopback mode. to test that the col pin is actually working, the BCM5222 can be placed into collision test mode. this mode is enabled by writing a 1 to bit 7 of the mii control regi ster. asserting txen causes the col output to go high, and deasserting txen causes t he col output to go low. while in loopback mode, several function bypass modes are also available that can provide a number of different combinations of feedback paths during loopback testing. these bypass modes include bypass scrambler, bypass mlt3 encoder and bypass 4b5b encoder. all bypass modes can be accessed by writing bits of the auxilia ry control register (10h). preliminary data sheet BCM5222 7/20/04 broadcom corporation document 5222-ds02-405-r full-duplex mode page 13 due to the nature of t he block rxdv mode (bit 9 of mii register 1bh), which is enabled by default, 10base- t loopback does not function properly. it is necessary to first disable the block rxdv mode by writ ing fd00h to the aux mode 2 register (1bh). f ull -d uplex m ode the BCM5222 supports full-duplex operation. while in full-du plex mode, a transc eiver can simultaneously transmit and receive packets on the cable. the col signal is never activa ted when in full-duplex mode. the crs output is asserted only during receive packets, not transmit packets. by default, the BCM5222 powers up in ha lf-duplex mode. when auto-negotiation is disabled, full-duplex operation can be enabled either by fdx pin control or by an mii register bit (register 0h, bit 8). when auto-negotiation is enabled in dte mode, full-duplex capability is advertised by default, but can be overridden by a write to the auto-negotiation advertisement register (04h). a uto -mdix the BCM5222 offers auto-mdix functioning on both phys. this enables the device to automatic ally adapt the configuration of the device transmit and rece ive pins in order to successfully link and transm it with a link partner. during auto-negotiation and 10/100base-tx operation, the BCM5222 normally transmits on td pins and receives on rd pins. the BCM5222 automatically switches it s transmitter to the rd pins and its receiver to the td pins, if required, in order to communicate with the remote device. if two devices are connected that both have auto-mdi/mdix crossover capability, then a random algorithm determines which end performs the crossover function. the auto-mdi/mdix crossover feature is a function of auto- negotiation. if the BCM5222 is configured not to perform auto- negotiation, the feature does not work, and a specific cable, either crossed or strai ght, is required to ensure the transmit function at one end of the cable is connect ed with the receive function at the other end of the cabl e. this feature is enabled by default, but can be disabled by setting the mdix_dis pin high during power-on reset. this will disable the function on both phys. by setting bit 11 in register 1c h to a 1, the auto-mdix can be disabled for an individual phy. during operation, the mdi state can be determined by reading bit 13 of register 1ch, as indicated in the BCM5222 data sheet. additionally, a manual mdi swap can be forced by setting or clearing bit 12 of register 1ch. 10base-t m ode the same magnetics module used in 100base-tx mode can be us ed to interface to the twis ted-pair cable when operating in 10base-t mode. the data is two-level manchester encoded inst ead of three-level ml t3, and no scrambling/ descrambling or 4b5b coding is performed. data and clock rate s are decreased by a factor of 10, with the mii interface signals operating at 2.5 mhz. BCM5222 preliminary data sheet 7/20/04 broadcom corporation page 14 10base-t serial mode document 5222-ds02-405-r 10base-t s erial m ode the BCM5222 supports 10base-t serial mode, also known as the 7-wire interface. in this mode, 10base-t transmit and receive packets appear at the mii in serial fashion, at a rate of 10 mhz. receive packet data is output on rxd0 synchronously with rxc. transmit packet data must be input on txd0 synchronously with txc. both clocks toggle at 10 mhz. the 10base-t serial mode is enabled by writing a 1 to bit 1 of the auxiliary multiple-phy register (1eh). this mode is not available in 100base-tx mode. table 4 on page 14 shows the mii pins used in this mode and their direction of operation. s pecial led m odes f orce led s o n the spdled , lnkled , actled , and fdxled outputs can be forced on (0 value) by writing a 01 to bit 5 and 4 of shadow register 1ah. d isable led s the spdled , lnkled , actled , and fdxled outputs can be forced off (1 value) by writing a 10 to bit 5 and 4 of shadow register 1ah. i nterrupt m ode the BCM5222 can be programmed to provid e an interrupt output that is shared between the two phys. three conditions can cause an interrupt to be generated: ch anges in the duplex mode, changes in the speed of operation or changes in the link status. the interrupt feature is dis abled by default and is enabled by sett ing mii register 1ah, bit 14. the intr pin is open-drain and can be wire-ored with intr pins of other chips on a board. the stat us of each interrupt source is reflected in register 1ah, bits 1, 2 and 3. if any type of interrupt occurs, the interrupt status bit, register 1ah, bit 0, is set. table 4: 10base-t serial mode (7-wire) signals pin label type description txd0 i serial transmit data txc o transmit data clock (10 mhz) txen i transmit enable rxd0 o serial receive data rxc o receive data clock (10 mhz) crs o carrier sense col/rxen o collision detect preliminary data sheet BCM5222 7/20/04 broadcom corporation document 5222-ds02-405-r power saving modes page 15 the interrupt register (1ah) also contains several bits to co ntrol different facets of the in terrupt function. if the interrupt enable bit is set to 0, no status bits are set and no interrupts are generated. if the interrupt enable bit is set to 1, the following conditions apply: ? if mask status bits (bits 9,10,11) are set to 0 and the interrupt mask (bit 8) is se t to 0, status bits and interrupts are available. ? if mask status bits (bits 9,10,11) are set to 0 and the interrupt mask (bit 8) is set to 1, status bits are set but no interrup ts generated. ? if any mask status bit is set to 1 and the interrupt mask is se t to 0, that status bit is not set and no hardware interrupt of that type is generated. ? if any mask status bit is set to 1 and the interrupt mask is set to 1, that status bit is not set and no interrupt of any kind is generated. p ower s aving m odes several power saving modes are implemented in the BCM5222. table 5 shows low power modes available in the BCM5222. low power modes can be achieved either by hardware pin or mi i register programming. the table shows both hardware pin and software bits that determine the low power modes and whether the BCM5222 keeps the clocks active. the BCM5222 requires a hard reset to return to normal mode from a low powe r mode if the clocks are not running. allow at least 2 ms before resuming normal operation with th e BCM5222 after the device is set to run in normal mode from a low power mode. table 5: low power modes hardware settings software setting chip operation low_pwr reset force iddq low_pwr mode enable clock clocks auto mdix comment 1 0 x 1 x off no reset state. 0 1 0 0 x on avail normal operation without any power saving modes active. x x 1 x x off no force iddq register serves as a software induced power-down mode. 1 1 0 0 0 off no low power mode without clk functioning, induced through hardware. 1 1 0 0 1 on avail low power mode with clk functioning, induced through hardware. 0 1 0 1 0 off no low power mode without clk functioning, induced through software. 0 1 0 1 1 on avail low power mode with clk functioning, induced through software. low_pwr: pin 27 (active high) reset : pin 68 (active low) force iddq: bit 0 of shadow register 1ah (0 ? normal op. 1 ? power down) low power mode: bit 1 of shadow register 1ah(0 ? normal op. 1 ? low power mode) enable clock: bit 2 of shadow register 1ah(0 ? disabled in lp mode 1 ? enabled) clock operation: if clock is off, additional power is saved. auto-mdix operation: only available if device has clock running. x=1/0 or don?t care BCM5222 preliminary data sheet 7/20/04 broadcom corporation page 16 register summary document 5222-ds02-405-r section 5: register summary m edia i ndependent i nterface (mii) m anagement i nterface : r egister p rogramming the BCM5222 fully complies with the ieee 802.3u media ind ependent interface (mii) specif ication. the mii management interface registers are serially written to and read from us ing the mdio and mdc pins. a single clock waveform must be provided to the BCM5222 at a rate of 0? 25mhz through the mdc pin. the serial data is communicated on the mdio pin. every mdio bit must have the same period as the mdc clock. the mdio bits are latched on the rising edge of the mdc clock. see table 6 for the fields in every mii instruction?s read or write packet frame. p reamble (pre) 32 consecutive 1 bits must be sent through the mdio pin to the BCM5222 to signal th e beginning of an mii instruction. fewer than 32 1 bits causes the remainder of the instruction to be ignored, unless t he preamble suppression mode is enabled (register 01, bit 6). s tart of f rame (st) a 01 pattern indicates that the start of the instruction follows. o peration c ode (op) a read instruction is indicated by 10, whil e a write instruction is indicated by 01. phy a ddress (phyad) a 5-bit phy address follows next, with the msb transmitte d first. the phy address allows a single mdio bus to access multiple transceivers. the BCM5222 supports the full 32-phy address space. r egister a ddress (regad) a 5-bit register address follows, with t he msb transmitted first. t he register map of the BCM5222, containing register addresses and bit definitions, are provided on the following pages. table 6: mii management frame format operation pre st op phyad regad ta data idle direction read 1 ... 1 01 10 aaaaa rrrrr zz z0 z...z d ... d z z driven to BCM5222 driven by BCM5222 write 1 ... 1 01 01 aaaaa rrrrr 10 d ... d z driven to BCM5222 preliminary data sheet BCM5222 7/20/04 broadcom corporation document 5222-ds02-405-r mii control register page 17 t urnaround (ta) the next two bit times are used to avoid contention on the mdio pin when a read operation is performed. for a write operation, 10 must be sent to the chip during these two bit times. for a read operation, the mdio pin must be placed into high-impedance during these two bit times. the chip dr ives the mdio pin to 0 during the second bit time. d ata the last 16 bits of the frame are the act ual data bits. for a write o peration, these bits are sent to the BCM5222. for a read operation, these bits are driven by the BCM5222. in either case, the msb is transmitted first. when writing to the BCM5222, the data field bits must be stab le 10 ns before the rising-edge of mdc, and must be held valid for 10 ns after the rising edge of mdc. when reading from the BCM5222, the data field bits are valid after the rising edge of mdc until the next ri sing edge of mdc. i dle a high-impedance state of the mdio line. all drivers are disabled and the phy?s pull-up resistor pulls the line high. at least one or more clocked idle states are required between frames. following are two examples of mii write and read instructions. to put a chip with phy address 00001 into loopback m ode, the following mii write instruction must be issued: 1111 1111 1111 1111 1111 1111 1111 1111 0101 00001 00000 10 0100 0000 0000 0000 1... to determine whether a phy is in the link pass stat e, the following mii read instruction must be issued: 1111 1111 1111 1111 1111 1111 1111 1111 0110 00001 00001 zz zzzz zzzz zzzz zzzz 1... for the mii read operation, the BCM5222 drives the mdio line du ring the ta and data fields (the last 17 bit times). a final 65 th clock pulse must be sent to close the transaction and cause a write operation. mii c ontrol r egister the mii control register bit descriptions are shown in table 7 . table 7: mii control register (address 00000b, 0d, 00h) bit name r/w description default 15 reset r/w (sc) 1 = phy reset 0 = normal operation 0 14 loopback r/w 1 = loopback mode 0 = normal operation 0 13 forced speed selection r/w 1 = 100 mbps 0 = 10 mbps 1 12 auto-negotiation enable r/w 1 = auto-negotiation enable 0 = auto-negotiation disable 1 11 power down ro 0 = normal operation 0 BCM5222 preliminary data sheet 7/20/04 broadcom corporation page 18 mii control register document 5222-ds02-405-r r eset to reset the BCM5222 by software control, a 1 must be writte n to bit 15 of the control regist er using an mii write operation. the bit clears itself after the reset process is complete, and need not be cleared using a seco nd mii write. writes to other control register bits has no effect until the reset pr ocess is completed, which requires approximately 1 s. writing a 0 to this bit has no effect. since this bit is self -clearing, within a few cycles after a writ e operation, it re turns a 0 when read. l oopback the BCM5222 may be placed into loopback mode by writing a 1 to bit 14 of the control register. clear the loopback mode by writing a 0 to bit 14 of the control register, or by resetting the chip. when this bit is read, it returns a 1 when the chip is in loopback mode, otherwise it returns a 0. f orced s peed s election if auto-negotiation is enabl ed (both auto-negotiation pin and bi t are enabled) or disabled by hardware control (auto- negotiation pin is pulled-low), this bit has no effect on the speed selection. however, if auto-negotiation is enabled by hardware, but is disabled by so ftware control, the o perating speed of the BCM5222 can be forced by writing the appropriate value to bit 13 of the control register. in this state, the speed is not affected by the f100 hardware pin. writing a 1 to this bit forces 100base-tx operation, while writing a 0 forces 10base-t operation. when this bi t is read, it returns the value of the software-controlled forced speed selection on ly. to read the overall state of forced speed selection, including both hardware and software control, use bit 2 of the auxiliary control register (18h). a uto -n egotiation e nable auto-negotiation can be disabled by one of two methods: hardware or software control. if the anen input pin is driven to a logic 0, auto-negotiation is disabled by hardware control. if bi t 12 of the control register is written with a value of 0, auto - negotiation is disabled by software control. when auto-negotiati on is disabled in this manner, writing a 1 to the same bit of the control register or resetting the chip re-enables auto-nego tiation. writing to this bit ha s no effect when auto-negotiation has been disabled by hardware control. when read, this bit return s the value most recently written to this location, or 1 if it has not been written since the last chip reset. 10 isolate r/w 1 = electrical ly isolate phy from mii 0 = normal operation 0 9 restart auto-negotiation r/w (sc) 1 = restart auto-negotiation process 0 = normal operation 0 8 duplex mode r/w 1 = full-duplex 0 = half-duplex 0 7 collision test enable r/w 1 = enable the collision test mode 0 = disable the collision test mode 0 6:0 reserved ro ignore when read 0 note: r/w = read/write, ro = read only, sc = self clear, ll = latched low, lh = latched high (ll and lh are cleared after read operation) table 7: mii control register (address 00000b, 0d, 00h) bit name r/w description default preliminary data sheet BCM5222 7/20/04 broadcom corporation document 5222-ds02-405-r mii control register page 19 p ower d own the power modes of the BCM5222 are not accessible by this mii register bit. use shadow register control instead. i solate the phy can be isolated from its media i ndependent interface by writing a 1 to bit 10 of the control regi ster. all mii outputs are tri-stated and all mii inputs are i gnored. because the mii management interfac e is still active, the isolate mode can be cleared by writing a 0 to bit 10 of the control register, or by resetting the chip. when this bit is read, it returns a 1 when the chip is in isolate mode; otherwise it returns a 0. r estart a uto -n egotiation bit 9 of the control register is a self-clearing bit that allows the auto-negotiation process to be restarted, regardless of th e current status of the auto- negotiation state machine. for this bit to have an effect, auto-negotiation must be enabled. writing a 1 to this bit restarts the auto-negotiation, while writing a 0 to this bit has no effect. because the bit is self-clearing af ter only a few cycles, it always returns a 0 when read. the operation of this bit is identical to bit 8 of the auxiliary multiple phy re gister (1eh). duplex mode this bit is logically or'd with the hardware pin, fdx, whenever auto-negotiation is disabled. c ollision t est test the col pin by activating the collision test mode. while in this mode, asserting txen causes the col output to go high within 512 bit times. deasserting txen caus es the col output to go low within 4 bit ti mes. writing a 1 to bit 7 of the control register enables the collision test mode. wr iting a 0 to this bit or resetting the chip disables the collision test mode. when this bit is read, it returns a 1 when the collision test mode has been enabled; otherwise it returns a 0. this bit should only be set while in loopback test mode. r eserved b its all reserved mii register bits must be written as 0 at all time s. ignore the BCM5222 output when these bits are read. BCM5222 preliminary data sheet 7/20/04 broadcom corporation page 20 mii status register document 5222-ds02-405-r mii s tatus r egister the mii status register bit descriptions are shown in table 8 . 100base-t4 c apability the BCM5222 is not capable of 100base-t4 operation, and re turns a 0 when bit 15 of the status register is read. 100base-tx f ull -d uplex c apability the BCM5222 is capable of 100base-tx full-duplex operation, and returns a 1 when bit 14 of the status register is read. 100base-tx h alf -d uplex c apability the BCM5222 is capable of 100base-tx half -duplex operation, and returns a 1 when bit 13 of the status register is read. 10base-t f ull -d uplex c apability the BCM5222 is capable of 10base-t full-duplex operation, an d returns a 1 when bit 12 of th e status register is read. table 8: mii status register (address 00001b, 01d, 01h) bit name r/w description default 15 100base-t4 capability ro 0 = not 100base-t4 capable 0 14 100base-tx fdx capability ro 1 = 100base-tx full-duplex capable 1 13 100base-tx capability ro 1 = 100base-tx half-duplex capable 1 12 10base-t fdx capability ro 1 = 10base-t full-duplex capable 1 11 10base-t capability ro 1 = 10base-t half-duplex capable 1 10:7 reserved ro ignore when read ignore when read 0 6 mf preamble suppression r/w 1 = preamble may be suppressed 0 = preamble always required 0 5 auto-negotiation complete ro 1 = auto-negotiation process completed 0 = auto-negotiation process not completed 0 4 remote fault ro 1 = far-end fault condition detected 0 = no far-end fault condition detected 0 3 auto-negotiation capability ro 1 = auto-negotiation capable 1 2 link status ro ll 1 = link is up (link pass state) 0 = link is down (link fail state) 0 1 jabber detect ro ll 1 = jabber condition detected 0 = no jabber condition detected 0 0 extended capability ro 1 = extended register capable 1 note: r/w = read/write, ro = read only, sc = self clear, ll = latched low, lh = latched high (ll and lh are cleared after read operation) preliminary data sheet BCM5222 7/20/04 broadcom corporation document 5222-ds02-405-r mii status register page 21 10base-t h alf -d uplex c apability the BCM5222 is capable of 10base-t half-d uplex operation, and returns a 1 when bi t 11 of the status register is read. r eserved b its ignore the BCM5222 output when these bits are read. p reamble s uppression this bit is the only writable bit in the status register. settin g this bit to a 1 allows subsequent mii management frames to be accepted with or without the st andard preamble pattern. when preamble suppre ssion is enabled, only 2 preamble bits are required between successive management commands, instead of the normal 32. a uto -n egotiation c omplete returns a 1 if auto-negotiation process has been completed and the contents of register s 4, 5, and 6 are valid. r emote f ault the phy returns a 1 on bit 4 of the status register when it s link partner has signalled a far-end fault condition. when a far- end fault occurs, the bit is latched at 1 and remains so until the register is read and the remote fault condition has been cleared. a uto -n egotiation c apability the BCM5222 is capable of performing ieee auto-negotiation, and returns a 1 when bit 4 of the status register is read, regardless of whether the auto-negot iation function has been disabled. l ink s tatus the BCM5222 returns a 1 on bit 2 of the status register when t he link state machine is in link pass, indicating that a valid link has been established. other wise, it returns 0. when a link failure occurs after the link pass state has been entered, the link status bit is etched at 0 and remains so until the bit is read. after the bit is read, it becomes 1 when the link pass sta te is entered again. j abber d etect 10base-t operation only. the BCM5222 returns a 1 on bit 1 of the status register if a jabber condition has been detected. after the bit is read once, or if the chip is reset, it reverts to 0. e xtended c apability the BCM5222 supports extended capability registers, and returns a 1 when bit 0 of the status register is read. several extended registers have been im plemented in the BCM5222, and their bit fu nctions are defined later in this section. BCM5222 preliminary data sheet 7/20/04 broadcom corporation page 22 phy identifier registers document 5222-ds02-405-r phy i dentifier r egisters the physical indentifier registers bit descriptions are shown in table 9 . broadcom corporation has been issued an organizationally unique identifier (oui) by the ieee. it is a 24-bit number, 00- 10-18, expressed as hex values. that number, along with the broadcom model number for the BCM5222 part, 32h, and broadcom revision number (n), is placed into two mii regi sters. the translation from oui, model number and revision number to phy identifier re gister occurs as follows: ? phyid high [15:0] = oui[21:6] ? phy low [15:0] = oui[5:0] + model[5:0] + rev[3:0] the 2 most significant bits of the oui are not repres ented (oui[23:22]). table 9 shows the result of concatenating these values to form mii identifier registers phyid high and phyid low. a uto -n egotiation a dvertisement r egister table 9: phy indentifier registers (addresses 00010 and 00011b, 02 and 03b, 02 and 03h) bit name r/w description value 15:0 mii address 02h ro phyid high 0040h 15:0 mii address 03h ro phyid low 632n (hex) note: the revision number (n) changes with each silicon revision. table 10: auto-negotiation advertisement register (address 04d, 04h) bit name r/w description default 15 next page r/w 1 = next page ability is enabled 0 = next page ability is disabled 0 14 reserved ro ignore when read 13 remote fault r/w 1 = tr ansmit remote fault 0 12:11 reserved ro ignore when read 00 10 pause r/w 1 = pause operation for full-duplex 0 9 advertise 100base-t4 ro 0 = do not advertise t4 capability 0 8 advertise 100base-tx fdx r/w 1 = advertise 100base-tx full-duplex 0 = do not advertise 100base-tx full-duplex 1 7 advertise 100base-tx r/w 1 = advertise 100base-tx 1 6 advertise 10base-t fdx r/w 1 = advertise 10base-t full-duplex 0 = do not advertise 10base-t full-duplex 1 note: r/w = read/write, ro = read only, sc = self clear, ll = latched low, lh = latched high, ll & lh clear after read operation. use default values of reserved bit(s) when writing to reserved bit(s). preliminary data sheet BCM5222 7/20/04 broadcom corporation document 5222-ds02-405-r auto-negotiation advertisement register page 23 n ext p age writing a 1 to bit 15 of the advertisement register enables the next page functioning. writing a 0 to this bit or resetting the chip clears the next page enable bit. this bit returns the value last written to it, or else 0 if no write has been completed s ince the last chip reset. r eserved b its ignore output when read. r emote f ault writing a 1 to bit 13 of the advertisement re gister causes a remote fault indicator to be sent to the link partner during auto- negotiation. writing a 0 to this bit or resetting the chip clears the remote fault transmission bit. this bit returns the value last written to it, or else 0 if no write has been completed since the last chip reset. r eserved b its ignore output when read. p ause pause operation for full-duplex links. the use of this bit is independent of the negotiat ed data rate, medium, or link technology. the setting of this bit indicates the availability of additional dte capability when full-duplex operation is in us e. this bit is used by one mac to communicate pause capability to its link partner and has no effect on phy operation. a dvertisement b its use bits 9:5 of the advertisement register to customize the ab ility information transmitted to the link partner. the default value for each bit reflects the abilities of the BCM5222. by writing a 1 to any of the bits, the corresponding ability can be transmitted to the link partner. writing a 0 to any bit caus es the corresponding ability to be suppressed from transmission. resetting the chip restores the default bit values. reading the r egister returns the values last written to the corresponding bits, or else the default values if no write has been completed since the last chip reset. s elector f ield bits 4:0 of the advertisement register co ntain the value 00001, indicating that the chip belongs to the 802.3 class of phy transceivers. 5 advertise 10base-t r/w 1 = advertise 10base-t 1 4:0 advertise selector field r/w indicates 802.3 00001 table 10: auto-negotiation advertisement register (address 04d, 04h) (cont.) bit name r/w description default note: r/w = read/write, ro = read only, sc = self clear, ll = latched low, lh = latched high, ll & lh clear after read operation. use default values of reserved bit(s) when writing to reserved bit(s). BCM5222 preliminary data sheet 7/20/04 broadcom corporation page 24 auto-negotiation link partner (lp) ability register document 5222-ds02-405-r a uto -n egotiation l ink p artner (lp) a bility r egister the values contained in the auto-negotiation link partner ability register are only guaranteed to be valid after auto- negotiation has successfully co mpleted, as indicated by bit 5 of the mii status register. lp n ext p age bit 15 of the link partner ability register returns a value of 1 when the link partner implements the next page function and has next page information that it wants to transmit. lp a cknowledge bit 14 of the link partner ability register is used by auto-negot iation to indicate that a device has successfully received its link partner?s link code word. lp r emote f ault bit 13 of the link partner ability register returns a value of 1 when the link partner signals that a remote fault has occurred . the BCM5222 simply copies the value to this register and do es not act upon it. reserved bits ignore when read. lp advertise pause indicates that the link partner pause bit is set. table 11: auto-negotiation link part ner ability register (address 05d, 05h) bit name r/w description default 15 lp next page ro link partner next page bit 0 14 lp acknowledge ro link partner acknowledge bit 0 13 lp remote fault ro link part ner remote fault indicator 0 12:11 reserved ro ignore when read 00 10 lp advertise pause ro link partner has pause capability 0 9 lp advertise 100base-t4 ro link pa rtner has 100base- t4 capability 0 8 lp advertise 100base-tx fdx ro link pa rtner has 100base-tx fdx capability 0 7 lp advertise 100base-tx ro link pa rtner has 100base- tx capability 0 6 lp advertise 10base-t fdx ro link pa rtner has 10base-t fdx capability 0 5 lp advertise 10base-t ro link partner has 10base-t capability 0 4:0 link partner selector field ro link partner selector field 00000 note: r/w = read/write, ro = read only, sc = self clear, ll = latched low, lh = latched high, ll & lh clear after read operation. use default values of reserved bit(s) when writing to reserved bit(s). preliminary data sheet BCM5222 7/20/04 broadcom corporation document 5222-ds02-405-r auto-negotiation expansion register page 25 lp advertise bits bits 9:5 of the link partner ability regi ster reflect the abilities of the link partner . a 1 on any of these bits indicates tha t the link partner is capable of performing the corresponding mode of operation. bits 9:5 are cleared any time auto-negotiation is restarted or the BCM5222 is reset. lp selector field bits 4:0 of the link partner ability register reflect the value of the link partner?s selector field. these bits are cleared an y time auto-negotiation is restarte d or the chip is reset. a uto -n egotiation e xpansion r egister table 14 shows the auto-negotiation expansion register bit descriptions. r eserved b its ignore when read. p arallel d etection f ault bit 4 of the auto-negotiation expansion register is a read-only bit that gets latched high when a parallel detection fault occu rs in the auto-negotiation state mach ine. for further details, refer to the ieee sta ndard. the bit is reset to 0 after the registe r is read, or when the chip is reset. l ink p artner n ext p age a ble bit 3 of the auto-negotiation expansion register returns a 1 w hen the link partner has next page capabilities. it has the same value as bit 15 of the link partner ability register. table 12: auto-negotiation expansion register (address 00110b, 6d, 06h) bit name r/w description default 15:5 reserved ro ignore when read 4 parallel detection fault ro lh 1 = parallel detection fault 0 = no parallel detection fault 0 3 link partner next page able ro 1 = link partner has next page capability 0 = link partner does not have next page 0 2 next page able ro 1 = BCM5222 does have next page capability 1 1 page received ro 1 = new page has been received 0 = new page has not been received 0 0 link partner auto- negotiation able ro lh 1 = link partner has auto-negotiation capability 0 = link partner does not have auto-negotiation 0 note: r/w = read/write, ro = read only, sc = self clear, ll = latched low, lh = latched high (ll and lh are cleared after read operation) BCM5222 preliminary data sheet 7/20/04 broadcom corporation page 26 auto-negotiation next page register document 5222-ds02-405-r n ext p age a ble the BCM5222 returns 1 when bit 2 of the auto-negotiation expans ion register is read, indicating that it has next page capabilities. p age r eceived bit 1 of the auto-negotiation expansion regi ster is latched high when a new link code word is received from the link partner, checked, and acknowledged. it remains high until the register is read, or until the chip is reset. l ink p artner a uto -n egotiation a ble bit 0 of the auto-negotiation expansion register returns a 1 when the link partner is known to have auto-negotiation capability. before any auto-negotiation in formation is exchanged, or if the link par tner does not comply with ieee auto- negotiation, the bit returns a value of 0. a uto -n egotiation n ext p age r egister n ext p age indicates whether this is the last next page to be transmitted. m essage p age differentiates a message page from an unformatted page. table 13: next page transmit register (address 07d, 07h) bit name r/w description default 15 next page r/w 1 = additional next page(s) will follow 0 = last page 0 14 reserved r/w ignore when read 0 13 message page r/w 1= message page 0 = unformatted page 1 12 acknowledge 2 r/w 1 = will comply with message 0 = cannot comply with message 0 11 toggle ro 1 = previous value of the transmitted link code word equalled logic zero 0 = previous value of the transmitted link code word equalled logic one 0 10:0 message/unformatted code field r/w 1 note: r/w = read/write, ro = read only, sc = self clear, ll = latched low, lh = latched high, ll & lh clear after read operation. use default values of reserved bit(s) when writing to reserved bit(s). preliminary data sheet BCM5222 7/20/04 broadcom corporation document 5222-ds02-405-r auto-negotiation link partner (lp) next page transmit register page 27 a cknowledge 2 indicates that a device has the ability to comply with the message. t oggle used by the arbitration function to ensure synchroni zation with the link partner during next page exchange. m essage c ode f ield an 11-bit-wide field, encoding 2048 possible messages. u nformatted c ode f ield an 11-bit-wide field, which may contain an arbitrary value. a uto -n egotiation l ink p artner (lp) n ext p age t ransmit r egister n ext p age indicates whether this is the last next page. table 14: next page transmit register (address 08d, 08h) bit name r/w description default 15 next page ro 1 = additional next page(s) will follow 0 = last page 0 14 reserved ro ignore when read 0 13 message page ro 1= message page 0 = unformatted page 0 12 acknowledge 2 ro 1 = will comply with message 0 = cannot comply with message 0 11 toggle ro 1 = previous value of the transmitted link code word equalled logic zero 0 = previous value of the transmitted link code word equalled logic one 0 10:0 message/unformatted code field ro 0 note: r/w = read/write, ro = read only, sc = self clear, ll = latched low, lh = latched high, ll & lh clear after read operation. use default values of reserved bit(s) when writing to reserved bit(s). BCM5222 preliminary data sheet 7/20/04 broadcom corporation page 28 100base-tx auxiliary control register document 5222-ds02-405-r m essage p age differentiates a message page from an unformatted page. a cknowledge 2 indicates that link part ner has the ability to comply with the message. t oggle used by the arbitration function to ensure synchroni zation with the link partner during next page exchange. m essage c ode f ield an 11-bit-wide field, encoding 2048 possible messages. u nformatted c ode f ield an 11-bit-wide field, which may contain an arbitrary value. 100base-tx a uxiliary c ontrol r egister table 15: 100base-tx auxiliary co ntrol register (address 16d, 10h) bit name r/w description default 15:14 reserved write as 0, ignore when read 0 13 transmit disable r/w 1 = transmitter disabled in phy 0 = normal operation 0 12:11 reserved r/w write as 0, ignore when read 00 10 bypass 4b5b encoder/ decoder r/w 1 = transmit and receive 5b codes over mii pins 0 = normal mii interface 0 9 bypass scrambler/ descrambler r/w 1 = scrambler and descrambler disabled 0 = scrambler and descrambler enabled 0 8 bypass nrzi encoder/ decoder r/w 1 = nrzi encoder and decoder is disabled 0 = nrzi encoder and decoder is enabled 0 7 bypass receive symbol alignment r/w 1 = 5b receive symbols not aligned 0 = receive symbols aligned to 5b boundaries 0 6 baseline wander correction disable r/w 1 = baseline wander correction disabled 0 = baseline wander correction enabled 0 5:0 reserved r/w write as 0, ignore when read 00000 note: r/w = read/write, ro = read only, sc = self clear, ll = latched low, lh = latched high, ll & lh clear after read operation. use default values of reserved bit(s) when writing to reserved bit(s). preliminary data sheet BCM5222 7/20/04 broadcom corporation document 5222-ds02-405-r 100base-tx aux iliary control register page 29 t ransmit d isable the transmitter can be disabled by writing a 1 to bit 13 of mii regi ster 10h. the transmitter output (td) is forced into a hig h impedance state. b ypass 4b5b e ncoder /d ecoder the 4b5b encoder and decoder can be bypasse d by writing a 1 to bit 10 of mii regist er 10h. the transmitter sends 5b codes from the txer and txd[3:0] pins directly to the scrambler. txen must be active and frame encapsulation (insertion of j/k and t/r codes) is not performed. the rece iver places descrambled and aligned 5b codes onto the rxer and rxd[3:0] pins. crs can be asserted when a valid frame is received. b ypass s crambler /d escrambler the stream cipher function can be disabled by writing a 1 to bi t 9 of mii register 1 0h. the stream cipher function is re-enable d by writing a 0 to this bit. b ypass nrzi e ncoder /d ecoder the nrzi encoder and decoder can be bypa ssed by writing a 1 to bit 8 of mii r egister 10h, causing 3-level nrz data to be transmitted and received on the cable. normal operation (3-level nrzi encoding and decoding) can be re-enabled by writing a 0 to this bit. b ypass r eceive s ymbol a lignment receive symbol alignment can be bypassed by writing a 1 to bi t 7 of mii register 10h. when used in conjunction with the bypass 4b5b encoder/decoder bit, unaligned 5b codes are placed directly on the rxer and rxd[3:0] pins. b aseline w ander c orrection d isable the baseline wander correction circuit can be disabled by writi ng a 1 to bit 6 of mii register 10h. the BCM5222 corrects for baseline wander on the receive data signal when this bit is cleared. r eserved b its the reserved bits of the 100base- tx auxiliary control re gister must be written as 0 at all times. ignore the BCM5222 outputs when these bits are read. BCM5222 preliminary data sheet 7/20/04 broadcom corporation page 30 100base-tx auxiliary status register document 5222-ds02-405-r 100base-tx a uxiliary s tatus r egister l ocked the phy returns a 1 in bit 9 when the descrambler is lo cked to the incoming data stream. otherwise it returns a 0. c urrent 100base-tx l ink s tatus the phy returns a 1 in bit 8 when the 100base-tx link status is good. otherwise it returns a 0. r emote f ault the phy returns a 1 while its link partner is signalling a far-end fault condition. otherwise it returns a 0. f alse c arrier d etected the phy returns a 1 in bit 5 of the extended status register if a false carrier has been detected since the last time this regi ster was read. otherwise it returns a 0. table 16: 100base-x auxiliary status register (address 17d, 11h) bit name r/w description default 15:10 reserved ro ignore when read 00h 9 locked ro 1 = descrambler locked 0 = descrambler unlocked 0 8 current 100base-x link status ro 1 = link pass 0 = link fail 0 7 remote fault ro 1 = remote fault detected 0 = no remote fault detected 0 6 reserved ro ignore when read 0 5 false carrier detected ro lh 1 = false carrier detected since last read 0 = no false carrier since last read 0 4 bad esd detected ro lh 1 = esd error detected since last read 0 = no esd error since last read 0 3 receive error detected ro lh 1 = receive error detected since last read 0 = no receive error since last read 0 2 transmit error detected ro lh 1 = transmit error code received since last read 0 = no transmit error code received since last read 0 1 lock error detected ro lh 1 = lock error detected since last read 0 = no lock error since last read 0 0 mlt3 code error detected ro lh 1 = mlt3 code error detected since last read 0 = no mlt3 code error since last read 0 note: r/w = read/write, ro = read only, sc = self clear, ll = latched low, lh = latched high, ll & lh clear after read operation. use default values of reserved bit(s) when writing to reserved bit(s). preliminary data sheet BCM5222 7/20/04 broadcom corporation document 5222-ds02-405-r 100base-tx receive error counter page 31 b ad esd d etected the phy returns a 1 in bit 4 if an end of stream delimiter e rror has been detected since the last time this register was read. otherwise it returns a 0. r eceive e rror d etected the phy returns a 1 in bit 3 if a packet was received with an invalid code since the last time th is register was read. otherwis e it returns a 0. t ransmit e rror d etected the phy returns a 1 in bit 2 if a packet was received with a transmit error code since the last time this register was read. otherwise it returns a 0. l ock e rror d etected the phy returns a 1 in bit 1 if the descrambl er has lost lock since the last time this register was read. otherwise it returns a 0. mlt3 c ode e rror d etected the phy returns a 1 in bit 0 if an mlt3 coding error has been detected in the receive data stream since the last time this register was read. othe rwise it returns a 0. 100base-tx r eceive e rror c ounter r eceive e rror c ounter [15:0] this counter increments each time the BCM5222 receives a non -collision packet containing at least one receive error. the counter automatically clears itself when read. when the counter reaches its maximum value, ffh, it stops counting receive errors until cleared. table 17: 100base-tx receive error counter (address 18d, 12h) bit name r/w description default 15:0 receive error counter [15:0] r/w number of non-collision packets with receive errors since last read 0000h BCM5222 preliminary data sheet 7/20/04 broadcom corporation page 32 100base-tx false carrier sense counter document 5222-ds02-405-r 100base-tx f alse c arrier s ense c ounter f alse c arrier s ense c ounter [7:0] this counter increments each time the BCM5222 detects a fa lse carrier on the receive input. this counter automatically clears itself when read. when the counter reaches its maximu m value, ffh, it stops count ing false carrier sense errors until cleared. a uxiliary c ontrol /s tatus r egister the auxiliary control/st atus register bit descriptions are shown in table 19 . table 18: 100base-tx false carrier sense counter (address 19d, 13h) bit name r/w description default 15:8 reserved ro ignore these bits 00h 7:0 false carrier sense counter [7:0] r/w number of false carrier se nse events since last read 00h table 19: auxiliary control/status register (address 11000b, 24d, 18h) bit name r/w description default 15 jabber disable r/w 1 = jabber function disabled 0 = jabber function enabled 0 14 force link r/w 1 = force link pass 0 = normal link operation 0 13:9 reserved ro ignore when read 000000 8 10m transmit power mode r/w 1 = 10base-t full power mode 0 = 10base-t low power mode 0 7:6 hsq : lsq r/w these two bits define the squelch mode of the 10base-t carrier sense mechanism 00 = normal squelch 01 = low squelch 10 = high squelch 11 = not allowed 00 5:4 edge rate [1:0] r/w 00 = 1 ns 01 = 2 ns 10 = 3 ns 11 = 4 ns 11 3 auto-negotiation indication ro 1 = auto-negotiation activated 0 = speed forced manually anen pin 2 force 100/10 indication ro 1 = speed forced to 100base-tx 0 = speed forced to 10base-t 1 speed indication ro 1 = 100base-tx 0 = 10base-t 0 full-duplex indication ro 1 = full-duplex active 0 = full-duplex not active preliminary data sheet BCM5222 7/20/04 broadcom corporation document 5222-ds02-405-r auxiliary control/status register page 33 j abber d isable 10base-t operation only. bit 15 of the auxiliary control register allows the user to disable the jabber detect func tion, define d in the ieee standard. this function sh uts off the transmitter when a transmission request has exceeded a maximum time limit. by writing a 1 to bit 15 of the auxiliary control register , the jabber detect function is disabled. writing a 0 to this bit or resetting the chip restores normal operation. reading this bit returns the value of jabber detect disable. f orce l ink writing a 1 to bit 14 of the auxiliary cont rol register allows the user to disable th e link integrity stat e machines, and place the BCM5222 into forced link pass status. writing a 0 to this bit or resetting the chip restores th e link integrity functions. read ing this bit returns the value of the force link bit. 10m t ransmit p ower m ode writing a 1 to bit 8 of the auxiliary co ntrol register allows the user to enable the 10base-t full power mode. writing a 0 to this bit or resetting the chip restores the setting to the 10base-t low power mode. hsq and lsq extend or decrease the squelch levels for detection of incoming 10baset data packets. the default squelch levels implemented are those defined in the ieee standard. the high-a nd low-squelch levels are useful for situations where the ieee-prescribed levels are inadeq uate. the squelch le vels are used by the crs/link block to filter out noise and recognize only valid packet preambles and link integrity pulses. extending the squelch levels allows th e BCM5222 to operate properly over longer cable lengths. decreasing the squelch levels can be useful in situations where there is a high level of noise present on the cables. reading these 2 bits returns the value of the squelch levels. e dge r ate control bits used to program the tran smit dac output edge rate in both 10base- t and 100base-tx mode . a larger value on these bits produces slower transitions on the transmit waveform. a uto -n egotiation i ndication this read-only bit indicates whether auto-negotiation has be en enabled or disabled on the BCM5222. a combination of a 1 in bit 12 of the control register and a logic 1 on the anen input pin is required to enable auto-negotiation. when auto- negotiation is disabled, bit 3 of the auxiliary control regist er (18h) returns a 0. at all other times, it returns a 1. f orce 100/10 i ndication this read-only bit returns a value of 0 when one of following cases is true: ? the anen pin is low and the f100 pin is low. ? the anen pin is high and bit 12 of the control register has been wr itten 0 and bit 13 of the control register has been written 0. BCM5222 preliminary data sheet 7/20/04 broadcom corporation page 34 auxiliary status summary register document 5222-ds02-405-r when bit 2 of the auxiliary control register (18h) is 0, the speed of the chip is 10 base-t. in all other ca ses, either the spee d is not forced (auto-negotiation is enabled), or the speed is forced to 100base-tx. s peed i ndication this read-only bit shows the true curr ent operation speed of the BCM5222. a 1 indicates 100base-tx operation, and a 0 indicates 10base-t. while the auto-negot iation exchange is performed, the bc m5222 is always ope rating at 10base-t speed. f ull -d uplex i ndication this read-only bit returns a 1 when the BCM5222 is in full-duplex mode. in all other modes, it returns a 0. a uxiliary s tatus s ummary r egister the auxiliary status summary register c ontains copies of redundant status bits found elsewhere within the mii register space. descriptions for each of these individual bits can be found associated with their primary register descriptions. table 20 indicates the bits found in this register. table 20: auxiliary status summary register (address 11001b, 25d, 19h) bit name r/w description default 15 auto-negotiation complete ro 1 = auto-negotiation process completed 0 14 auto-negotiation complete acknowledge ro lh 1 = auto-negotiation completed acknowledge state 0 13 auto-negotiation acknowledge detected ro lh 1 = auto-negotiation acknowledge detected 0 12 auto-negotiation ability detect ro lh 1 = auto-negotiation for link partner ability 0 11 auto-negotiation pause ro BCM5222 and link partner pause operation bit 0 10:8 auto-negotiation hcd ro 000 = no highest common denominator 001 = 10base-t 010 = 10base-t full-duplex 011 = 100base-tx 100 = 100base-t4 101 = 100base-tx full-duplex 11x = undefined 000 7 auto-negotiation parallel detection fault ro lh 1 = parallel detection fault 0 6 link partner remote fault ro 1 = link partner remote fault 0 5 link partner page received ro lh 1 = new page has been received 0 4 link partner auto- negotiation able ro 1 = link partner is auto-negotiation capable 0 3 speed indicator ro 1 = 100 mbps 0 = 10 mbps preliminary data sheet BCM5222 7/20/04 broadcom corporation document 5222-ds02-405-r interrupt register page 35 i nterrupt r egister i nterrupt e nable writing a 1 to bit 14 of the interrupt register will enable the in terrupt function. by writing to bits [11:8] of the interrupt register, the intr pin will signal when the corresponding interrupt events occur. writing a 0 to bit 14, or resetting the device will disable the interrupt function. fdx m ask when this bit is set, changes in duplex mode will not generate a hardware or software interrupt. 2 link status ro ll 1 = link is up (link pass state) 0 1 auto-negotiation enabled ro 1 = auto-negotiation enabled anen pin 0 jabber detect ro lh 1 = jabber condition detected 0 note: r/w = read/write, ro = read only, sc = self clear, ll = latched low, lh = latched high (ll and lh are cleared after read operation) table 21: interr upt register (address 26d, 1ah) bit name r/w description default 15 reserved r/w ignore when read 0 14 intr enable r/w interrupt enable 0 13:12 reserved ro ignore when read 00 11 fdx mask r/w full-duplex interrupt mask 1 10 spd mask r/w speed interrupt mask 1 9 link mask r/w link interrupt mask 1 8 intr mask r/w master interrupt mask 1 7:4 reserved ro ignore when read 0000 3 fdx change ro lh duplex change interrupt 0 2 spd change ro lh speed change interrupt 0 1 link change ro lh link change interrupt 0 0 intr status ro lh interrupt status 0 note: r/w = read/write, ro = read only, sc = self clear, ll = latched low, lh = latched high, ll & lh clear after read operation. use default values of reserved bit(s) when writing to reserved bit(s). table 20: auxiliary status summary re gister (address 11001b, 25d, 19h) (cont.) bit name r/w description default BCM5222 preliminary data sheet 7/20/04 broadcom corporation page 36 auxiliary mode 2 register document 5222-ds02-405-r spd m ask when this bit is set, changes in operating speed will not generate a a hardware or software interrupt. l ink m ask when this bit is set, changes in link status will not generate a a hardware or software interrupt. i nterrupt m ask master interrupt mask. when this bit is set, no interrupts will be hardware gener ated, regardless of th e state of the other mask bits. fdx c hange a ?1? indicates a change of duplex status since la st register read. regist er read clears the bit. spd c hange a ?1? indicates a change of speed status since la st register read. regist er read clears the bit. l ink c hange a ?1? indicates a change of link status since la st register read. register read clears the bit. i nterrupt s tatus represents status of the intr pin. a ?1? indicates that the interrupt mask is off and that one or more of the change bits are set. a register read clears the bit. a uxiliary m ode 2 r egister table 22: auxiliary mode 2 register (address 27d, 1bh) bit name r/w description default 15:12 reserved ro ignore when read 0 11 10bt dribble bit correct r/w 1 = enable, 0 = disable 0 10 jumbo packet enable r/w 1 = enable, 0 = disable 0 9 reserved r/w write as 0, ignore when read 00 8 txc invert r/w 1= invert clock 0 7 block 10bt echo mode r/w 1 = enable, 0 = disable 1 6:4 reserved r/w write as 0, ignore when read 000 preliminary data sheet BCM5222 7/20/04 broadcom corporation document 5222-ds02-405-r auxiliary mode 2 register page 37 10bt d ribble b it c orrect when enabled, the phy rounds down to the nearest nibble w hen dribble bits are present on the 10base-t input stream. j umbo p acket e nable writing a 1 to this bit enables jumbo sized packets to be received and transmitted. txc i nvert writing a 1 to bit 8 of the auxiliary mo de 2 register will invert the txc clock. b lock 10bt e cho m ode when enabled, during 10base-t half-duplex transmit operation, the txen signal does not echo onto the rxdv pin. the txen echoes onto the crs pin and the crs deassertion directly follows the txen deassertion. q ualified p arallel d etect m ode this bit allows the auto-negotiation/para llel detection process to be qualified with in formation in the adve rtisement register. if this bit is not set, the local BCM5222 device is enabled to auto-negotiate. if the far-end device is a 10base-t or 100base- tx non-auto-negotiating legacy type, the local device auto-n egotiate/parallel detects the far- end device, regardless of the advertisement register (04h) contents. if this bit is set, the local device compares the link speed de tected to the contents of its advertisement register. if the particular link speed is enabled in the ad vertisement register, the local device asse rts link. if the link speed is disabled in this register, then the local device does not assert link and continues monitoring for a matching capability link speed. 3 reserved r/w write as 1, ignore when read 1 2 reserved r/w write as 0, ignore when read 0 1 qual parallel detect mode r/w 1 = enable, 0 = disable 1 0 reserved ro ignore when read 0 note: r/w = read/write, ro = read only, sc = self clear, ll = latched low, lh = latched high, ll & lh clear after read operation. use default values of reserved bit(s) when writing to reserved bit(s). table 22: auxiliary mode 2 register (address 27d, 1bh) bit name r/w description default BCM5222 preliminary data sheet 7/20/04 broadcom corporation page 38 10base-t auxiliary error and general status register document 5222-ds02-405-r 10base-t a uxiliary e rror and g eneral s tatus r egister mdix s tatus when read as a 1, this bit indicates that the BCM5222 has its mdi td+ and rd+ signals swapped either due to manually setting mdix swap bit to a 1 or through hp auto-mdix functi on if it is enabled and the BCM5222 has detected a mdi cross- over cable. mdix m anual s wap when this bit is set to a 1, the BCM5222 forces its mdi td+ and rd+ signals to be swapped. hp a uto -mdix d isable when this bit is set to a 1, then the BCM5222 disables the hp auto-mdix function. table 23: 10base-t auxiliary error & general status register (address 28d, 1ch) bit name r/w description default 15:14 reserved ro ignore when read 0 13 mdix status ro 0 = mdi is in use 1 = mdix is in use 0 12 mdix manual swap rw 0 = mdi or mdix if mdix is not disabled 1 = force mdix 0 11 hp auto-mdix disable r/w 0 = enable hp auto-mdix 1 = disable hp auto-mdix 0 10 manchester code error ro 1 = manchester code error (10base-t) 0 9 end of frame error ro 1 = eo f detection error (10base-t) 0 8:4 reserved ro ignore when read 00000 3 auto-negotiation indication ro 1 = auto-negotiation activated 0 = speed forced manually 1 2 force 100/10 indication ro 1 = speed forced to 100base-tx 0 = speed forced to 10base-t 1 1 speed indicati on ro 1 = 100base-tx 0 = 10base-t 0 0 full-duplex indication ro 1 = full-duplex active 0 = full-duplex not active 0 note: all error bits in the auxiliary error and general status register are read-only and ar e latched high. when certain types of errors occur in the BCM5222, one or more correspondin g error bits become ?1?. they remain so until the register is read, or until a chip reset occurs. all such errors necessa rily result in data errors, and are indicated by a high value on the rxer output pin at the time the error occurs. r/w = read/write, ro = read only, sc = self clear, ll = latched low, lh = latched high, ll & lh clear after read operation. use default values of reserved bit(s) when writing to reserved bit(s). preliminary data sheet BCM5222 7/20/04 broadcom corporation document 5222-ds02-405-r 10base-t auxiliary e rror and general status register page 39 m anchester c ode e rror indicates that a manchester code vi olation was received. this bit is only valid during 10base-t operation. e nd of f rame e rror indicates that the end of frame (eof) sequence was improperly re ceived, or not received at all. this error bit is only valid during 10base-t operation. a uto -n egotiation i ndication this read-only bit indicates whether auto-negotiation has be en enabled or disabled on the BCM5222. a combination of a 1 in bit 12 of the control register and a logic 1 on the anen input pin is required to enable auto-negotiation. when auto- negotiation is disabled, bit 15 of the auxiliary mode regi ster returns a 0. at all ot her times, it returns a 1. f orce 100/10 i ndication this read-only bit returns a value of 0 when one of following two cases is true: ? the anen pin is low and the f100 pin is low. (or) ? bit 12 of the control register has been written 0 a nd bit 13 of the control r egister has been written 0. when bit 2 of the auxiliary control register is 0, the speed of the chip is 10base-t . in all other cases, either the speed is not forced (auto-negotiation is enabled), or the speed is forced to 100base-tx. s peed i ndication this read-only bit shows the true current operation speed of the BCM5222. a 1 bit indicates 100base-tx operation, while a 0 indicates 10base-t. while the auto-negotiation exchange is performed, the BCM5222 is always operating at 10base- t speed. f ull -d uplex i ndication this read-only bit returns a 1 when the BCM5222 is in fu ll-duplex mode. in all other modes, it returns a 0. BCM5222 preliminary data sheet 7/20/04 broadcom corporation page 40 auxiliary mode register document 5222-ds02-405-r a uxiliary m ode r egister table 24 shows the bit descrip tions for the auxiliary mode register. l ink led d isable when set to 1, disables the link led output pin. when 0, link led output is enabled. b lock txen m ode when this mode is enabled, short ipgs of 1, 2, 3 or 4 txc cycles results in t he insertion of two idles before the beginning of the next packet?s jk symbols. a uxiliary m ultiple phy r egister table 24: auxiliary mode register (address 11101b, 29d, 1dh) bit name r/w description default 15:5 reserved ro ignore when read 4 reserved r/w write as 0, ignore when read 0 3 link led disable r/w 1 = disable link led output 0 = enable link led output 0 2 reserved ro ignore when read 0 1 block txen mode r/w 1 = enable block txen mode 0 = disable block txen mode 0 0 reserved ro ignore when read 0 table 25: auxiliary multiple phy register (address 30d, 1eh) bit name r/w description default 15 hcd_tx_fdx ro 1 = auto-negotiation re sult is 100base-tx full-duplex 0 14 hcd_t4 ro 1 = auto-negotiation result is 100base-t4 0 13 hcd_tx ro 1 = auto-negotiation result is 100base-tx 0 12 hcd_10base-t_fdx ro 1 = auto-negotiation result is 10base-t full-duplex 0 11 hcd_10base-t ro 1 = auto-negotiation result is 10base-t 0 10:9 reserved ro ignore when read 00 8 restart auto-negotiation r/w (sc) 1 = restart auto-negotiation process 0 = (no effect) 0 7 auto-negotiation complete ro 1 = auto-negotiation process completed 0 = auto-negotiation process not completed 0 6 acknowledge complete ro 1 = auto-negotiation acknowledge completed 0 note: r/w = read/write, ro = read only, sc = self clear, ll = latched low, lh = latched high, ll & lh clear after read operation. use default values of reserved bit(s) when writing to reserved bit(s). preliminary data sheet BCM5222 7/20/04 broadcom corporation document 5222-ds02-405-r auxiliary multiple phy register page 41 hcd b its bits 15:11 of the auxiliary multiple phy register are 5 r ead-only bits that report the hi ghest common denominator (hcd) result of the auto-negotiation process. immediately upon entering the link pass state after each reset or restart auto- negotiation, only 1 of these 5 bits is 1. the link pass state is identified by a 1 in bit 6 or 7 of this register. the hcd bits are reset to 0 every time auto-negotiation is restarted or the bcm52 22 is reset. for their intended application, these bits uniquel y identify the hcd only after the first link pass after reset or re start of auto-negotiation. on la ter link fault and subsequent re- negotiations, if the ability of the link partner is different, more than 1 of the above bits can be active. r estart a uto -n egotiation this self-clearing bit allows the auto-negotiation process to be restarted, regardless of the current status of the state machine. for this bit to work, auto-negotiation must be enabled. writing a 1 to this bit restar ts auto-negotiation. since the b it is self-clearing, it always returns a 0 wh en read. the operation of this bit is i dentical to bit 9 of the control register. auto-negotiation complete this read-only bit returns a 1 after the auto-negotiation pr ocess has been completed. it remains 1 until the auto-negotiation process is restarted, a link fault occurs, or the chip is reset. if auto-negotiation is disabled or the process is still in pro gress, the bit returns a 0. a cknowledge c omplete this read-only bit returns a 1 after the acknowledgment exchange portion of the auto- negotiation process has been completed and the arbitrator state machine has exited the comp lete acknowledge state. it re mains this value until the auto- negotiation process is restarted, a link fault occurs, auto-negotiation is disabled, or the BCM5222 is reset. a cknowledge d etected this read-only bit is set to 1 when the arbitrator state mach ine exits the acknowledged detect st ate. it remains high until the auto-negotiation process is restarted, or the BCM5222 is reset. 5 acknowledge detected ro 1 = auto-negotiation acknowledge detected 0 4 ability detect ro 1 = auto-negotiation waiting for lp ability 0 3 super isolate r/w 1 = super isolate mode 0 = normal operation 0 2 reserved ro ignore when read 0 1 10base-t serial mode r/w 1 = enable 10base-t serial mode 0 = disable 10base-t serial mode 0 0 reserved r/w write as 0, ignore when read 0 table 25: auxiliary multiple phy register (address 30d, 1eh) bit name r/w description default note: r/w = read/write, ro = read only, sc = self clear, ll = latched low, lh = latched high, ll & lh clear after read operation. use default values of reserved bit(s) when writing to reserved bit(s). BCM5222 preliminary data sheet 7/20/04 broadcom corporation page 42 broadcom test register document 5222-ds02-405-r a bility d etect this read-only bit returns a 1 when the auto-negotiation state ma chine is in the ability detect state. it enter s this state a specified time period after the auto-negotiati on process begins, and exits after the fi rst flp burst or link pulses are detecte d from the link partner. this bit returns a 0 any time the auto- negotiation state machine is not in the ability detect state. s uper i solate writing a 1 to this bit places the BCM5222 into the super isolat e mode. similar to the isolate mode, all mii inputs are ignored , and all mii outputs are tri-stated. additionally, all link pulses are suppressed. this allows the BCM5222 to coexist with another phy on the same adapter card, with only one being activated at any time. 10base-t s erial m ode writing a 1 to bit 1 of the auxiliary mode register enables the 10base-t se rial mode. in the normal 10base-t mode of operation, as defined by the mii standard, transmit and receive data packets trav erse the txd[3:0] and rxd[3:0] busses at a rate of 2.5 mhz. in the special 10b ase-t serial mode, data packets traverse to the mac layer across only txd0 and rxd0 at a rate of 10 mhz. serial opera tion is not available in 100base-tx mode. b roadcom t est r egister s hadow r egister e nable writing a 1 to bit 7 of register 1fh al lows r/w access to the shadow registers. table 26: broadcom test (address 31d, 1fh) bit name r/w description default 15:8 reserved ro ignore when read 00h 7 shadow register enable r/w 1 = enable shadow registers 0 = disable shadow registers 0 6 reserved ro ignore when read 0 5 reserved r/w write as 0, ignore when read 0 4:0 reserved r/w write as 0bh, ignore when read 0bh note: r/w = read/write, ro = read only, sc = self clear, ll = latched low, lh = latched high, ll & lh clear after read operation. use default values of reserved bit(s) when writing to reserved bit(s). preliminary data sheet BCM5222 7/20/04 broadcom corporation document 5222-ds02-405-r auxiliary mode 4 register (shadow register) page 43 a uxiliary m ode 4 r egister (s hadow r egister ) f orce led [1:0] the spdled , lnkled , actled and fdxled outputs can be forced to on state (0) by writing a value of 01 to force led [1:0]. these leds can be forced to off state (1 ) by writing a value of 10 to force led {1:0]. e nable c lock d uring l ow p ower if this bit is set to a 1 then the clocks are running in low mode. f orce iddq m ode if this bit is set to a 1, then the bcm52 22 enters iddq mode. when the device is in iddq mode, everything is disabled. the BCM5222 requires a hard reset to return to normal mode. table 27: auxiliary mode 4 regi ster (shadow register 26d, 1ah) bit name r/w description default 15:6 reserved r/w write as 30h, ignore when read 30h 5:4 force led [1:0] r/w 01 = force all led status to on 0 state 10 = force all led status to off 1 state 00 3 reserved r/w write as 0, ignore when read 0 2 enable clock during low power r/w 0 = disables clock during low power modes 1 = enables clock during low power modes 0 1 force low power mode r/w 0 = normal operation 1 = forces the 5222 to enter the low power mode 0 0 force iddq mode r/w 0 = normal operation 1 = causes the BCM5222 to go to iddq mode 0 note: r/w = read/write, ro = read only, sc = self clear, ll = latched low, lh = latched high, ll & lh clear after read operation. use default values of reserved bit(s) when writing to reserved bit(s). mii shadow register bank 1 is accessed by setting mii register 1fh bit 7 to a 1. BCM5222 preliminary data sheet 7/20/04 broadcom corporation page 44 auxiliary status 2 register (shadow register) document 5222-ds02-405-r a uxiliary s tatus 2 r egister (s hadow r egister ) mlt3 d etected the BCM5222 returns a 1 in this bit whenever mlt3 signaling is detected. c able l ength 100x [2:0] the BCM5222 provides the cable length for eac h port when a 100tx link is established. adc p eak a mplitude [5:0] the BCM5222 returns the ad converter?s 6- bit peak amplitude seen during this link. table 28: auxiliary status 2 register (shadow register 27d, 1bh) bit name r/w description default 15 mlt3 detected r/o 1 = mlt3 detected 0h 14:12 cable length 100x [2:0] r/o the BCM5222 shows the cable length in 20 meters increment as shown in the table below 000 11:6 adc peak amplitude [5:0] r/o a to d peak amplitude seen 00h 5:0 reserved r/w write as 0, ignore when read 01h note: r/w = read/write, ro = read only, sc = self clear, ll = latched low, lh = latched high, ll & lh clear after read operation. use default values of reserved bit(s) when writing to reserved bit(s). mii shadow register bank 1 is accessed by setting mii register 1fh bit 7 to a 1. table 29: cable length cable length 100x [2:0] cable length in meters 000 < 20 001 20 to <40 010 40 to <60 011 60 to < 80 100 80 to < 100 101 100 to < 120 110 120 to < 140 111 > 140 preliminary data sheet BCM5222 7/20/04 broadcom corporation document 5222-ds02-405-r auxiliary status 3 register (shadow register) page 45 a uxiliary s tatus 3 r egister (s hadow r egister ) n oise [7:0] the BCM5222 provides the current mean squared error value for noise when a valid link is established. fifo c onsumption [3:0] the BCM5222 indicates the number of nibbles of fifo currently used. a uxiliary m ode 3 r egister (s hadow r egister ) fifo s ize s elect [3:0] the BCM5222 indicates the current selection of rece ive fifo size using bit 3 through 0 as shown in table 32 . table 30: auxiliary status 3 register (shadow register 28d, 1ch) bit name r/w description default 15:8 noise [7:0] r/o current mean square error value, valid only if link is established 00h 7:4 reserved r/w write as 0, ignore when read 0h 3:0 fifo consumption [3:0] r/o currently ut ilized number of nibbles in the receive fifo 0000 note: mii shadow register bank 1 is accessed by setting mii register 1fh bit 7 to a 1 table 31: auxiliary mode 3 regi ster (shadow register 29d, 1dh) bit name r/w description default 15:4 reserved r/w write as 00h, ignore when read 000h 3:0 fifo size select [3:0] r/w current ly selected receive fifo size 4h note: r/w = read/write, ro = read only, sc = self clear, ll = latched low, lh = latched high, ll & lh clear after read operation. use default values of reserved bit(s) when writing to reserved bit(s). mii shadow register bank 1 is accessed by setting mii register 1fh bit 7 to a 1. table 32: current receive fifo size fifo size select [3:0] receive fifo size in use (# of bits) 0001 16 0010 20 0011 24 0100 28 BCM5222 preliminary data sheet 7/20/04 broadcom corporation page 46 auxiliary status 4 register (shadow register) document 5222-ds02-405-r a uxiliary s tatus 4 r egister (s hadow r egister ) p acket l ength c ounter [15:0] the BCM5222 shows the number bytes in the last packet receiv ed. this is valid only when a valid link is established. 0101 32 0110 36 0111 40 1000 44 1001 48 1010 52 1011 56 1100 60 1101 64 table 33: auxiliary status 4 register (shadow register 30d, 1eh) bit name r/w description default 15:0 packet length counter[15:0] r/o number of bytes in the last received packet 0000h table 32: current receive fifo size (cont.) fifo size select [3:0] receive fifo size in use (# of bits) preliminary data sheet BCM5222 7/20/04 broadcom corporation document 5222-ds02-405-r timing and ac characteristics page 47 section 6: timing and ac characteristics the timing information contained in this section applies to the BCM5222. all mii interface pins comply with ieee 802.3u timing specif ications (see reconciliation sublayer and media independent interface in ieee 802.3u timing specifications). all digita l output timing s pecified at c l = 30 pf. output rise/fall times measured between 10% and 90% of t he output signal swing. input rise/fall times measured between v il max. and v ih min. output signal transitions re ferenced to the midpoint of the output signal swing. input signal transitions referenced to the midpoint between v il max. and v ih min. see table 34 and table 35 for the timing parameters. see figure 4 for an illustration of clock and reset timing. figure 4: clock and reset timing table 34: clock timing parameter symbol min typical max unit xtali cycle time ck_cycl e 39.998 40 40.002 ns xtali high/low time ck_hi ck_lo 14 20 26 ns xtali rise/fall time ck_edge 4 ns table 35: reset timing parameter symbol min typical max unit reset pulse length with st able xtali input reset_len 400 ns activity after end of ha rdware reset reset_wait 100 s reset rise/fall time reset_edg e 10 ns xtali reset normal phy reset_len reset_wait ck_hi ck_cycle ck_edge ck_lo ck_edge activity begins here reset_edge reset_edge BCM5222 preliminary data sheet 7/20/04 broadcom corporation page 48 timing and ac characteristics document 5222-ds02-405-r table 36 provides the parameters for 100base-tx transmit timing. figure 5 illustrates the 100base-tx transmit start of packet timing and figure 6 shows the100base-tx transmit end of packet timing. figure 5: mii transmit start of packet timing (100base-tx) table 36: mii 100base-tx transmit timing parameter symbol min typical max unit txc cycle time 40 ns txc high/low time 16 20 24 ns txc rise/fall time 2 5 ns txen, txd[3:0] setup time to txc rising* txen_setup 10 ns txen, txd[3:0] hold time from txc rising* txen_hold 0 ns td after txen assert txen_tdata 60 140 ns txd to td steady state delay txd_tdata 60 100 ns crs assert after txen assert txen_crs 0 40 ns crs deassert after txen deassert txen_crs_eo p 0160ns col assert after txen a ssert (while rx) txen_col ns col deassert after txen deassert (while rx) txen_col_eo p ns txen, txd[3:0] setup ti me to xtali rising* 2 ns txen, txd[3:0] hold time from xtali rising* 10 ns 5 55 5 tx_tdata txen_crs txen_col txd_tdata ssd 3rd data nibble col * * when receive is concurrently active ii iij4 j3 j2 k4 k3 k2 k1 k0 crs td txer txen txd, j1 txen_setup i i i i i i i i i x j0 txen_hold xtali or txc preliminary data sheet BCM5222 7/20/04 broadcom corporation document 5222-ds02-405-r timing and ac characteristics page 49 figure 6: mii transmit end of packet timing (100base-tx) table 37 below provides 100base-x receive timing parameters. see figure7onpage50 and figure8onpage51 for illustrations of 100base-tx receive st art of packet timing parameters and 100b ase-tx receive end of packet timing. figure9onpage51 shows 100base-tx receive packet premature end. see figure 10 on page 52 for an illustration of link failure or stream cipher error during receive packet. 100base-tx false carrier sense timing is shown in figure 11 on page 52 . table 37: mii 100base-tx receive timing parameter symbol min typical max unit rxc cycle time 40 ns rxc high/low time (rxdv asserted) 16 20 24 ns rxc high time (rxdv deasserted) 20 ns rxc low time (rxdv deasserted) 20 ns rxc rise/fall time tbd ns rxdv, rxer, rxd[3:0] delay from rxc falling -4 4 ns crs deassert from rxc falling (valid eop only) tbd ns crs assert after rd rx_crs 200 ns crs deassert after rd (valid eop) rx_crs_eop 60 240 ns crs deassert after rd (premature end) rx_crs_idle 150 ns rxdv assert after rd rx_rxdv 160 ns rxdv deassert after rd ( valid eop) rx_rxdv_eop 200 ns rxdv assert after crs 60 ns rd to rxd steady state delay rx_rxd 180 ns col assert after rd (while tx) rx_col 200 ns col deassert after rd (valid eop) rx_col_eop 130 240 ns esd txen_crs_eop txen_col_eop last data data n t4 t3 t2 t1 t0 r4 r3 r2 r1 r0 nibble td txd, txer col txen crs i i i i x xtali or txc BCM5222 preliminary data sheet 7/20/04 broadcom corporation page 50 timing and ac characteristics document 5222-ds02-405-r figure 7: mii receive start of packet timing (100base-tx) col deassert after rd (premature end) rx_col_idle 130 240 ns note: rxc minimum high and low times are guaranteed when rxen is asserted or deasserted. the mii port will always tristate while rxen is low. table 37: mii 100base-tx receive timing (cont.) parameter symbol min typical max unit rx_crs rx_col 3rd data ssd rx_rxdv nibble * when transmit is active j4 j3 j2 k4 k3 k2 k1 k0 j1 j0 ii ii i i i 0 5 col* rxdv rxd, rd rxc crs rxer rxc_max_hi rxc_max_lo preliminary data sheet BCM5222 7/20/04 broadcom corporation document 5222-ds02-405-r timing and ac characteristics page 51 figure 8: mii receive end of packet timing (100base-tx figure 9: mii receive packet premature end (100base-tx) last data col rxdv rxd, rd rxc crs esd rx_crs_eop rx_col_eop n4 n3 n2 n1 n0 t4 t3 t2 t1 t0 r4 r3 r2 r1 r0 rxer nibble data n rx_rxd i i i i i i i i i i rx_rxdv_eop 0 rxen data i rxdv rxd rd rxc crs ii ii i i ii ii i i i i ii ii i i data error code (6) rx_crs_idle rx_col_idle rxer 0 BCM5222 preliminary data sheet 7/20/04 broadcom corporation page 52 timing and ac characteristics document 5222-ds02-405-r figure 10: mii link failure or stream cipher error during receive packet figure 11: mii false carrier sense timing (100base-tx) rxdv rxd rxc crs data error code (2 or 3) rxer link/ lock 0 0 rxdv rxd rd rxc crs rxer 0 e i i ii i i ii ii i i ii i i i i i i preliminary data sheet BCM5222 7/20/04 broadcom corporation document 5222-ds02-405-r timing and ac characteristics page 53 table 38 provides the parameters fo r 10base-t transmit timing. figure 12 illustrates 10base-t transmit start of timing packet. figure 12: mii 10base-t transmit start of packet timing table 39 provides the parameters for mii 10base-t receive timing. mii 10base-t collisi on timing is shown in table 40 . table 38: mii 10base-t transmit timing parameter symbol min typical max unit txc cycle time (10base-t) txc_cycle 400 ns txc high/low time (10base-t) 200 ns txc rise/fall time 2 5 ns txc rising edge to t xen valid txc_txen_vali d 25 ns txc rising edge to txen hold txc_txen_hold 75 ns txc rising edge to txd valid txc_txd_valid 25 ns txc rising edge to txd hold txc_txd_hold 75 ns td after txen assert txen_tdata 60 360 ns crs assert after txen assert txen_crs tbd tbd ns crs deassert after txen de assert txen_crs_eop tbd tbd ns col assert after txen a ssert (while rx) txen_col col deassert after txen deassert (while rx) txen_col_eop idle on twisted pair after txen de-assert tx_quiet 450 800 ns note: txd, txen delivered to the BCM5222 should be generated of the rising edge of txc. txc txen txc_txen_valid txc_txen_hold 10base-t mii input latch point 50 ns 5 txd crs txen_crs txc_txd_hold txc_txd_valid 400 ns BCM5222 preliminary data sheet 7/20/04 broadcom corporation page 54 timing and ac characteristics document 5222-ds02-405-r table 39: mii 10base-t receive timing parameter symbol min typical max unit rxc cycle time rxc_cycle 400 ns rxc high/low time 200 ns crs assert after receive analog data rx_crs_bt 300 ns rxc valid after crs assert rxc_valid 2000 ns rxdv assert after receive analog data rx_rxdv 2300 ns rxdv deassert after receive analog eop ends rx_not_rxdv 560 ns crs deassert after receive analog eop ends rx_not_crs 560 ns table 40: mii 10base-t collision timing parameter symbol min typical max unit col assert after receive analog (while transmitting) rx_col tbd ns col deassert after txen deassert (while receiving) txen_not_co l tbd ns col assert after txen assert (while receiving) txen_col tbd ns col deassert after receive analog ends (while transmitting) rx_not_col tbd ns table 41: 10base_t serial transmit timing parameter symbol min typical max unit txc cycle time txc 95 100 105 ns txc low time txc high time txc_lo txc_high 35 50 65 ns txc rise time txc fall time txc_rise txc_fall 210ns txen, txd0 to txc rising txen_setup 10 txen, txd0 hold after txc rising txen_hold 4 txen to td start txen_tdata 500 ns txen to td end txen_quiet 500 ns preliminary data sheet BCM5222 7/20/04 broadcom corporation document 5222-ds02-405-r timing and ac characteristics page 55 figure 13: 10base-t serial transmit timing table 42: 10base_t serial receive timing parameter symbol min typical max unit rxc cycle time rxc 95 100 105 ns rxc low time rxc high time rxc_lo rxc_high 35 50 65 ns rxc rise time rxc fall time rxc_rise rxc_fall 2 - 10ns rxc to rxd0 output delay rxd_delay 5 ns crs assert after rd rx_crs_dv 300 ns crs deassert after rd , valid eop rx_not_crs 560 ns txc_low txc_high txc_rise txc_fall txc txen txen_setup txen_hold txen_quiet txen_txdata txen_setup txen_hold td+/- BCM5222 preliminary data sheet 7/20/04 broadcom corporation page 56 timing and ac characteristics document 5222-ds02-405-r figure 14: 10base-t serial receive timing table 43 , table 44 , and table 45 provide the parameters for loopback timing, auto-negotiation timing, and led timing. table 43: loopback timing parameter symbol min typical max unit txd to rxd steady state propagation delay 250 ns table 44: auto-negotiation timing parameter symbol min typical max unit link test pulse width 100 ns flp burst interval 16 ms clock pulse to clock pulse 123 s clock pulse to data pulse (data = 1) 62.5 s table 45: led timing parameter symbol min typical max unit led on time (actled )80ms led off time (actled )80ms rxc rxd0 rxd_delay rd+/- rx_crs_bt rx_rxdv rx_not_crs preliminary data sheet BCM5222 7/20/04 broadcom corporation document 5222-ds02-405-r timing and ac characteristics page 57 management data interface timing parameters are described in table 46 . figure 15 and figure 16 illustrate two types of management interface timing. figure 15: management interface timing figure 16: management interface ti ming (with preamble suppression on) table 46: management data interface timing parameter symbol min typical max unit mdc cycle time 40 ns mdc high/low 20 ns mdc rise/fall time 10 ns mdio input setup time to mdc rising 10 ns mdio input hold time from mdc rising 4 ns mdio output delay from mdc rising 0 30 ns mdio (from BCM5222) mdc mdc_fall mdio_hold mdio_setup mdc_rise mdc_cycle mdio_setup mdio_hold mdio_delay mdio (into BCM5222 ) mdc skip skip d0 d1 hi-z (phy pull-up) idle s t mdio start of mdc/mdio cycle end of mdc/mdio cycle note: must wait two mdc clock cycles between mdio commands when preamble suppression is activated (mii register 1, bit 6 set to ?1?). BCM5222 preliminary data sheet 7/20/04 broadcom corporation page 58 electrical characte ristics document 5222-ds02-405-r section 7: electrical characteristics table 47 provides the absolute maximum ratings for the bcm5 222. the recommended operating conditions for the BCM5222 are shown in table 48 . table 49 provides the package th ermal characteristics. table51onpage59 gives the electrical characteristics of the BCM5222. table 47: absolute maximum ratings symbols parameter pin min max unit v dd supply voltage ovdd, biasvdd gnd - 0.3 3.465 v dvdd, avdd, pllavdd gnd - 0.3 1.89 v v i input voltage gnd - 0.3 ovdd + 0.3 v i i input current 10 ma note : these specifications indicate levels where permanent damage to the device may occur. functional operation is not guaranteed under these conditions. operat ion at absolute maximum conditions for extended periods may adversely affect long-term reliability of the device. table 48: recommended operating conditions for BCM5222 symbol parameter pin operating mode min max unit v dd supply voltage BCM5222 ovdd, biasvdd 3.135 3.465 v dvdd, avdd, pllavdd 1.71 1.89 v v ih high-level input voltage all digital inputs 2.0 ovdd v xtali 1.2 2.0 v v il low-level input voltage all digital inputs 0.8 v xtali 0 0.4 v v idiff differential input voltage rd 100base-tx 150 mv v icm common mode input voltage rd 3.3v center tap 1.85 2.05 v rd 2.5v center tap 1.15 1.35 v t a ambient operating temperature - 5222 -40 85 c table 49: package thermal characteristics (BCM5222kqm) ambient air temperature ja in still air (c) jb (c/w) jc (c/w) 70 56.96 61.73 40.28 table 50: package thermal characteristics (BCM5222kpf) ambient air temperature ja in still air (c) jb (c/w) jc (c/w) 70 41.00 15.68 25.56 preliminary data sheet BCM5222 7/20/04 broadcom corporation document 5222-ds02-405-r electrical characteristics page 59 table 51: electrical characteristics symbol parameter pins condition min typical max unit i dd supply current avdd, pl vdd, dvdd 100base-tx 109 ma biasvdd, ovdd hardware/ software 44 ma v oh high-level output voltage all digital outputs i oh = ? 12 ma ovdd -0.5 v td driving loaded magnetics module avdd +1.5 v v ol low-level output voltage all digital outputs i ol = 8 ma 0.4 v td driving loaded magnetics module avdd -1.5 v v odiff differential output voltage td 400 mv i i input current digital inputs w/ pull-up resistors v i = ovdd +100 a v i = dgnd -200 a digital inputs w/ pull-down resistors v i = ovdd +200 a v i = dgnd -100 a all other digital inputs dgnd v i ovdd + 100 a i oz high-impedance output current all three-state outputs dgnd v o ovdd a all open-drain outputs v o = ovdd a v bias bias voltage rdac 1.18 1.30 v note: current supplied through the center tap of the magnetics can be supplie d at either 2.5v or 3.3v. current sunk through the BCM5222 is 90ma. BCM5222 preliminary data sheet 7/20/04 broadcom corporation page 60 application example document 5222-ds02-405-r section 8: application example figure 17: BCM5222 1.8v and 3.3v power connections in 100 mqfp package ovdd ognd ovdd ovdd biasgnd ovdd biasvdd ovdd agnd dvdd agnd dvdd dgnd dgnd dgnd agnd ognd agnd pllagnd avdd ognd ovdd ognd pllavdd analog 1.8v digital 1.8v 3.3v 3.3v analog 1.8v 3.3v ferrite bead .1uf .1uf ferrite bead .1uf 2.2uf 1000pf .001uf 0.1uf .001uf BCM5222 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 .001uf ferrite bead 2.2uf 0.1uf 2.2uf preliminary data sheet BCM5222 7/20/04 broadcom corporation document 5222-ds02-405-r mechanical information page 61 section 9: mechanical information figure 18: 100-pin mqfp package BCM5222 preliminary data sheet 7/20/04 broadcom corporation page 62 mechanical information document 5222-ds02-405-r figure 19: 100-pin fbga package preliminary data sheet BCM5222 7/20/04 broadcom corporation document 5222-ds02-405-r ordering information page 63 section 10: ordering information part number package ambient temperature BCM5222kqm 100-mqfp, 14 mm x 20 mm -40 to 85 c -40 to 185 f BCM5222kpf a a. contact broadcom sales department for availability. 100-fbga, 9 mm x 9 mm -40 to 85 5222-ds02-405-rc -40 to 185 f document 5222-ds02-405-r broadcom corporation 16215 alton parkway p.o. box 57013 irvine, ca 92619-7013 phone: 949-450-8700 fax: 949-450-8710 broadcom ? corporation reserves the right to make changes without further notice to any products or data herein to improve reliability, f unction, or design. information furnished by broadcom corporation is believed to be accurate and reliable. however, broadcom corporation does not assume any liability arising out of the application or use of this information, nor the application or use of any prod uct or circuit described herein, neither does it convey any license under its patent rights nor the rights of others. BCM5222 preliminary data sheet 7/20/04 |
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